公开(公告)号：US20080247229A1

公开(公告)日：2008-10-09

申请号：US11771997

申请日：2007-06-29

申请人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu

发明人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5621 ,  G11C2211/5623 ,  G11C2211/5634 ,  G11C2211/565

摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

摘要翻译： 一种非易失性存储装置，其中对非易失性存储元件执行电流检测。 对第一非易失性存储元件的选定字线施加电压，并且将源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。 源极和p阱电压在相应的正直流电平下被调节，以避免地电压或电压波动，如果源电压至少在接地电压下被调节，则会发生接地反弹或电压波动。 通过感测非易失性存储元件的NAND串中的电流来确定非易失性存储元件的编程条件。 感觉可以快速发生，因为等待地面反弹稳定没有延迟。

公开(公告)号：US20140003176A1

公开(公告)日：2014-01-02

申请号：US13605424

申请日：2012-09-06

申请人： Man Lung Mui ,  Jongmin Park ,  Hao Thai Nguyen ,  Seungpil Lee

发明人： Man Lung Mui ,  Jongmin Park ,  Hao Thai Nguyen ,  Seungpil Lee

IPC分类号： G11C7/06

CPC分类号： G11C16/26 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3436

摘要： A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

摘要翻译： 介绍了一种适用于非易失性存储器电路的紧凑且通用的高速读出放大器。 感测放大器电路连接到第一和第二电源电平，用于设置位线上的编程禁止电平的第一电平和用于对用于感测操作的位线进行预充电的第二电平。 在数据锁存器之外，感测放大器只能使用NMOS晶体管。 电路的布置也允许同时对位线进行放电，将感测结果传送到其他锁存器。

公开(公告)号：US08300472B2

公开(公告)日：2012-10-30

申请号：US13178690

申请日：2011-07-08

申请人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee

发明人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee

IPC分类号： G11C16/26

CPC分类号： G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/26

摘要： In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.

摘要翻译： 在感测具有对应的一组感测模块的非易失性存储器单元的页面中，当识别出每个高电流单元时，它被锁定以进一步检测，而页面中的其他单元继续被感测。 被锁定的感测模块处于锁定模式并变为非活动状态。 当处于锁定模式时，来自感测模块的噪声源变得显着。 通过将其位线耦合到邻近单元，噪声容易干扰相邻单元的感测。 噪声也可以通过页面的公共源行耦合，以影响页面中单元格的持续感测的准确性。 改进的感测模块和方法将噪声与锁定感测模块隔离，以影响在页面中感测存储器单元中仍然有效的其他感测模块。

公开(公告)号：US20090323421A1

公开(公告)日：2009-12-31

申请号：US12163133

申请日：2008-06-27

申请人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

发明人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

IPC分类号： G11C16/06 ,  G11C5/14

CPC分类号： G11C16/0483 ,  G11C5/147 ,  G11C16/26

摘要： Accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different sense amps are strobed at different times. First and second sets of sense amps perform a sensing operation on respective storage elements, such as in an all bit line configuration. The first set of sense amps is strobed at a first time point. In response, a sensed analog level is converted to digital data. The A/D conversion relies on the sense amp supply voltage being accurate. To avoid a fluctuation in the sense amp supply voltage, a bypass path allows the storage elements associated with the first set of sense amps to continue to draw power from the sense amp supply voltage. The second set of sense amps is strobed at a later, second time point.

摘要翻译： 通过避免当在不同时间选通不同的感测放大器时可能发生的感测放大器电源电压的波动来改善存储器件中的读取或验证等感测操作的精度。 第一和第二组感测放大器对各个存储元件执行感测操作，例如以全位线配置。 第一组感测放大器在第一时间点选。 作为响应，将感测的模拟电平转换为数字数据。 A / D转换依赖于正确的读出放大器电源电压。 为了避免感测放大器电源电压的波动，旁路通路允许与第一组感测放大器相关联的存储元件继续从感测放大器电源电压获取功率。 第二组感测放大器在稍后的第二时间点被选通。

公开(公告)号：US20090296488A1

公开(公告)日：2009-12-03

申请号：US12128535

申请日：2008-05-28

申请人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

发明人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

IPC分类号： G11C16/26 ,  G11C7/00

CPC分类号： G11C16/26 ,  G11C7/02 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5634

摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

摘要翻译： 提供了用于感测并联感测的一组非易失性存储单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。 预充电电路耦合到用于将节点充电到初始电压的节点。 中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。 电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。 这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

公开(公告)号：US07539060B2

公开(公告)日：2009-05-26

申请号：US11771997

申请日：2007-06-29

申请人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu

发明人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5621 ,  G11C2211/5623 ,  G11C2211/5634 ,  G11C2211/565

摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

摘要翻译： 一种非易失性存储装置，其中对非易失性存储元件执行电流检测。 对第一非易失性存储元件的选定字线施加电压，并且将源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。 源极和p阱电压在相应的正直流电平下被调节，以避免地电压或电压波动，如果源电压至少在接地电压下被调节，则会发生接地反弹或电压波动。 通过感测非易失性存储元件的NAND串中的电流来确定非易失性存储元件的编程条件。 感觉可以快速发生，因为等待地面反弹稳定没有延迟。

公开(公告)号：US07471567B1

公开(公告)日：2008-12-30

申请号：US11772002

申请日：2007-06-29

申请人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

发明人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5645 ,  G11C2211/565

摘要： Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

摘要翻译： 在感测NAND串中所选择的非易失性存储元件的编程条件之前，位线对位线噪声在NAND串中放电。 施加源电压，其提高导电NAND串中的电压。 电压升高导致噪声与相邻NAND串的电容耦合。 电流下拉器件用于在执行感测之前对每个NAND串进行放电。 在每个NAND串被连接到放电路径达预定时间量之后，NAND串的位线被耦合到电压感测组件，用于基于位线的电位感测所选择的非易失性存储元件的编程状态 。 所选择的非易失性存储元件可具有负阈值电压。 此外，与所选择的非易失性存储元件相关联的字线可以被设置为接地。

公开(公告)号：US20080266964A1

公开(公告)日：2008-10-30

申请号：US11739509

申请日：2007-04-24

申请人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

发明人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3436

摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

摘要翻译： 解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。 在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。 在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。 也可以使用这些方法的各种组合。 在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。 还可以补偿向前的身体偏差。

公开(公告)号：US20080247253A1

公开(公告)日：2008-10-09

申请号：US11772018

申请日：2007-06-29

申请人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

发明人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

IPC分类号： G11C7/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5621 ,  G11C2211/5623 ,  G11C2211/5634 ,  G11C2211/565

摘要： A non-volatile storage system in which temperature compensation of a bit line voltage is provided during a sense operation of a non-volatile storage element. A gate voltage of a transistor which couples a bit line associated with the non-volatile storage element to a sense module is temperature-compensated so that it is higher when temperature is higher to compensate for variations with temperature of the bit line voltage. The bit line voltage, in turn, varies due to variations in temperature of a threshold voltage of the non-volatile storage element. The sense module determines a programming condition of the non-volatile storage element, which may be provided in a NAND string, by sensing a voltage. The sense operation may be a read operation, verify operation, or erase-verify operation, for instance. Further, the threshold voltage of the non-volatile storage element may be positive or negative. In another aspect, a source voltage is temperature compensated.

摘要翻译： 一种在非易失性存储元件的感测操作期间提供位线电压的温度补偿的非易失性存储系统。 将与非易失性存储元件相关联的位线耦合到感测模块的晶体管的栅极电压被温度补偿，使得当温度更高以补偿位线电压的温度变化时，栅极电压更高。 位线电压又由于非易失性存储元件的阈值电压的温度变化而变化。 感测模块​​通过感测电压来确定可以提供在NAND串中的非易失性存储元件的编程条件。 例如，感测操作可以是读取操作，验证操作或擦除验证操作。 此外，非易失性存储元件的阈值电压可以是正或负。 在另一方面，源电压被温度补偿。

公开(公告)号：US20080247239A1

公开(公告)日：2008-10-09

申请号：US11771992

申请日：2007-06-29

申请人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu

发明人： Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui ,  Shahzad Khalid ,  Hock So ,  Prashanti Govindu

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5621 ,  G11C2211/5623 ,  G11C2211/5634 ,  G11C2211/565

摘要： Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

摘要翻译： 在用于非易失性存储元件的非易失性存储设备中执行电流检测。 对第一非易失性存储元件的选定字线施加电压，并且将源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。 源极和p阱电压在相应的正直流电平下被调节，以避免地电压或电压波动，如果源电压至少在接地电压下被调节，则会发生接地反弹或电压波动。 通过感测非易失性存储元件的NAND串中的电流来确定非易失性存储元件的编程条件。 感觉可以快速发生，因为等待地面反弹稳定没有延迟。