公开(公告)号：US08219788B1

公开(公告)日：2012-07-10

申请号：US11933267

申请日：2007-10-31

申请人： Yu Qing Cheng ,  Peter N. Glaskowsky ,  Carlos Puchol ,  Seungyoon Peter Song

发明人： Yu Qing Cheng ,  Peter N. Glaskowsky ,  Carlos Puchol ,  Seungyoon Peter Song

IPC分类号： G06F9/00

CPC分类号： G06F9/455 ,  G06F9/4825 ,  Y02D10/24

摘要： A virtual core management system including a first physical core having a first utilization constraint, a second physical core having a second utilization constraint, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a utilization indicator configured to measure a utilization of the first physical core with respect to the first utilization constraint and measure a utilization of the second physical core with respect to the second utilization constraint, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the utilization of the first physical core and the utilization of the second physical core.

摘要翻译： 一种虚拟核心管理系统，包括具有第一利用约束的第一物理核心，具有第二利用约束的第二物理核心和包括与执行程序相关联的逻辑状态的集合的虚拟核心。 所述虚拟核心管理系统还包括利用指示器，其被配置为测量所述第一物理核心相对于所述第一利用约束的利用率并且测量所述第二物理核心相对于所述第二利用约束的利用率，以及虚拟核心管理组件 被配置为基于所述第一物理核心的利用和所述第二物理核心的利用中的至少一个来将所述虚拟核心映射到所述第一物理核心和所述第二物理核心之一。

公开(公告)号：US07788473B1

公开(公告)日：2010-08-31

申请号：US11646008

申请日：2006-12-26

申请人： Chris Nelson ,  Matthew Ashcraft ,  John Gregory Favor ,  Seungyoon Peter Song

发明人： Chris Nelson ,  Matthew Ashcraft ,  John Gregory Favor ,  Seungyoon Peter Song

IPC分类号： G06F9/30

CPC分类号： G06F9/383 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3861

摘要： Prediction of data values to be read from memory by a microprocessor for load operations. In one aspect, a method for predicting a data value that will result from a load operation to be executed by the microprocessor includes accessing an entry in a load value prediction table that stores a predicted data value corresponding to the load operation. The predicted data value is stored in a physical storage destination of the microprocessor to be available as a result of the load operation without waiting for execution of the load operation to complete. The storage destination is the destination for a loaded data value resulting from executing the load operation.

摘要翻译： 预测由微处理器从存储器读取的数据值以进行加载操作。 一方面，用于预测由微处理器执行的加载操作产生的数据值的方法包括访问存储与加载操作对应的预测数据值的载入值预测表中的条目。 预测数据值被存储在微处理器的物理存储目的地中，作为加载操作的结果可用，而不等待执行加载操作完成。 存储目的地是由执行加载操作产生的加载数据值的目的地。

公开(公告)号：US6094705A

公开(公告)日：2000-07-25

申请号：US266072

申请日：1999-03-10

申请人： Seungyoon Peter Song

发明人： Seungyoon Peter Song

IPC分类号： G11C11/406 ,  G11C11/403

CPC分类号： G11C11/406

摘要： A method and system for selective refresh for a memory array is disclosed. The method and system comprises providing a plurality of valid bits, each of the valid bits being associated with a row of the memory device; and detecting when data access is performed within a row of the device. The method and system further comprises setting the associated valid bit, the setting of the associated valid bit providing an indication that the row does not need to be refreshed for the refresh period. By providing the valid bits in the refresh controller and associating them with a row of the memory array then if a cell is written or read at least once a duration equivalent to a refresh period, then the cells do not need to be refreshed. When a DRAM cell is accessed (read or written), its charge is fully restored so that it does not need refresh for a duration equivalent to a refresh interval. In applications that use DRAMs to repeatedly write and read data, such as frame buffers in display systems, the DRAM cells may be accessed frequently enough so that the cells may not need to be refreshed at all. If the cells are written or read at least once in a duration equivalent to a refresh period, then they do not need to be refreshed. Accordingly, through the use of the present invention power consumption is significantly reduced.

摘要翻译： 公开了用于存储器阵列的选择性刷新的方法和系统。 该方法和系统包括提供多个有效位，每个有效位与存储器件的一行相关联; 以及检测何时在设备的行内执行数据访问。 该方法和系统还包括设置相关联的有效位，相关联的有效位的设置提供该行不需要刷新刷新周期的指示。 通过在刷新控制器中提供有效位并将它们与存储器阵列的行相关联，然后如果单元被写入或读取至少等于刷新周期的持续时间，那么单元不需要刷新。 当DRAM单元被访问（读取或写入）时，其电荷被完全恢复，使得它不需要刷新持续时间等于刷新间隔。 在使用DRAM重复写入和读取数据（例如显示系统中的帧缓冲器）的应用中，可以频繁地访问DRAM单元，使得单元可能根本不需要刷新。 如果单元在等于刷新周期的持续时间内写入或读取至少一次，则不需要刷新它们。 因此，通过使用本发明，功耗明显降低。

公开(公告)号：US5742802A

公开(公告)日：1998-04-21

申请号：US602653

申请日：1996-02-16

申请人： Ronald S. Harter ,  Gary Douglas Huber ,  Arturo Martin-de-Nicolas ,  Seungyoon Peter Song

发明人： Ronald S. Harter ,  Gary Douglas Huber ,  Arturo Martin-de-Nicolas ,  Seungyoon Peter Song

IPC分类号： G06F9/318 ,  G06F9/455

CPC分类号： G06F9/30174 ,  G06F9/3879 ,  G06F9/45504

摘要： The present invention provides a method and system for using hardware to assist software in emulating the guest instructions. The method and system comprises an emulation assist unit (EAU) which efficiently maps a guest instruction to a unique tag, an index, and an address of the corresponding semantic routine. The index determines where in a cache a plurality of tags are stored. A separate cache within the EAU stores each tag in association with the address the first time the corresponding guest instruction is emulated. Thus, the emulation assist unit also dynamically responds to the set of guest instructions being emulated. The first time a guest instruction is emulated, the EAU determines the address and stores the address in the cache in association with the tag. When the guest instruction is emulated again, the EAU uses the tag to access the stored addresses of the corresponding semantic routine.

摘要翻译： 本发明提供了一种使用硬件来辅助软件来仿真客户指令的方法和系统。 该方法和系统包括有效地将访客指令映射到唯一标签的仿真辅助单元（EAU），索引和相应语义例程的地址。 索引确定高速缓存中存储多个标签的位置。 EAU内的单独缓存器在第一次仿真相应的客户指令时，将与每个标签相关联的存储器存储在一起。 因此，仿真辅助单元还动态地响应被仿真的一组访客指令。 EAU第一次仿真客户指令时，EAU确定地址并将该地址与标签相关联存储在缓存中。 当客户指令再次被仿真时，EAU使用标签访问相应语义例程的存储地址。