公开(公告)号：US10579519B2

公开(公告)日：2020-03-03

申请号：US15746618

申请日：2015-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mark David Lillibridge ,  Gary Gostin ,  Paolo Faraboschi ,  Derek Alan Sherlock ,  Harvey Ray

IPC: G06F12/06 ,  G06F3/06

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

公开(公告)号：US10402113B2

公开(公告)日：2019-09-03

申请号：US15313690

申请日：2014-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Harvey Ray ,  Derek Alan Sherlock ,  Gregg B. Lesartre

IPC: G06F3/06 ,  G06F11/10

Abstract: According to an example, hierarchal stripe locks may be obtained for a source stripe and a destination stripe. In response to receiving data for the source stripe, the data is written from the source stripe to the destination stripe, and the hierarchal stripe locks are released for the source stripe and the destination stripe. In response to receiving the data-migrated token, the hierarchal stripe locks are released for the source stripe and the destination stripe.

公开(公告)号：US10394635B2

公开(公告)日：2019-08-27

申请号：US15324945

申请日：2014-10-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/40 ,  G06F12/06 ,  G06F12/1009

Abstract: A system includes a central processing unit (CPU) to process data. A first memory management unit (MMU) in the CPU generates an external request to a bus for data located external to the CPU. An external fault handler in the CPU processes a fault response received via the bus. The fault response is generated externally to the CPU and relates to a fault being detected with respect to the external request.

公开(公告)号：US10069745B2

公开(公告)日：2018-09-04

申请号：US15263228

申请日：2016-09-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Alan Sherlock ,  Gary B. Gostin

IPC: H04L12/823 ,  H04L12/863 ,  H04L12/24

Abstract: A lossy fabric transmitting device includes a queue, a link transmitter to transmit packets from the queue, a trigger mechanism to automatically discard a packet contained in the queue in response to satisfaction of a packet dropping threshold and a discard counter to track packets being discarded from the queue. The discard counter has a failure detection threshold. The discard counter resets in response to the link transmitter transmitting a packet. Satisfaction of the failure detection threshold identifies the link transmitter as being immediately adjacent a failed link of a lossy fabric.

公开(公告)号：US20250165425A1

公开(公告)日：2025-05-22

申请号：US18511801

申请日：2023-11-16

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Alan Sherlock ,  Joe P. Cowan ,  Frank R. Dropps ,  Gary B. Gostin

IPC: G06F13/40 ,  G06F13/38 ,  H04L49/104

Abstract: One aspect of the instant application can provide a networking device. The networking device can include a set of Compute Express Link (CXL) ports, a set of non-CXL ports, a set of bridge circuits associated with the set of CXL ports, and an interconnect. A respective bridge circuit can include a packet-conversion subcircuit to convert a CXL packet received at a corresponding CXL port to a customized packet and a protocol-conversion subcircuit to convert a CXL protocol to a customized protocol implemented by the networking device. The interconnect can switch customized packets among the CXL and non-CXL ports based on the customized protocol.

公开(公告)号：US20250119378A1

公开(公告)日：2025-04-10

申请号：US18412088

申请日：2024-01-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Alan Sherlock

IPC: H04L45/00 ,  H04L45/12 ,  H04L45/121 ,  H04L45/24

Abstract: A switching fabric uses traffic congestion information to inform its opportunistic use of non-minimal routes. An ingress port of a network switch collects traffic congestion information from the egress ports of the network switch. The traffic congestion information includes minimal and non-minimal route congestion metrics for the egress ports. Candidate egress ports for forwarding a packet to a destination node are identified. One of the candidate egress ports is selected based on the traffic congestion information. The selection process is biased to prefer some candidate egress ports over others. Particularly, the candidate egress ports that provide non-minimal routes to the destination node and have high minimal route congestion metrics are disfavored by the selection process.

公开(公告)号：US11909643B2

公开(公告)日：2024-02-20

申请号：US17473643

申请日：2021-09-13

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Alan Sherlock

IPC: H04L47/12 ,  H04L43/0876 ,  H04L43/16

CPC classification number: H04L47/12 ,  H04L43/0876 ,  H04L43/16

Abstract: A system for facilitating efficient progression management in a multi-source tracker of a responder device is provided. During operation, the system can maintain, in a memory device of the responder device, a first tracker for all requests and a second tracker for a privileged group of requests. The system can select a first group from a set of groups as the privileged group. If a request from a requesting device cannot be accepted into the first tracker, the system can determine whether the request belongs to the first group based on a header field of the request. If the request belongs to the first group, the system can select the request for accepting into the second tracker. Subsequently, when a respective request belonging to the first group has been accepted, the system can select a second group from the set of groups as the privileged group.

公开(公告)号：US20230262001A1

公开(公告)日：2023-08-17

申请号：US17672481

申请日：2022-02-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Frank R. Dropps ,  Joseph G. Tietz ,  Derek Alan Sherlock

IPC: H04L47/2441 ,  H04L47/2483 ,  H04L47/10 ,  H04L47/52 ,  H04L47/78

CPC classification number: H04L47/2441 ,  H04L47/39 ,  H04L47/521 ,  H04L47/781 ,  H04L47/2483

Abstract: A system for facilitating enhanced virtual channel switching in a node of a distributed computing environment is provided. During operation, the system can allocate flow control credits for a first virtual channel to an upstream node in the distributed computing environment. The system can receive, via a message path comprising the upstream node, a message on the first virtual channel based on the allocated flow control credits. The system can then store the message in a queue associated with an input port and determine whether the message is a candidate for changing the first virtual channel at the node based on a mapping rule associated with the input port. If the message is a candidate, the system can associate the message with a second virtual channel indicated in the mapping rule in the queue. Subsequently, the system can send the message from the queue on the second virtual channel.

公开(公告)号：US11314449B2

公开(公告)日：2022-04-26

申请号：US15929725

申请日：2020-05-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02

Abstract: In some examples, a tracker receives a write request that is acknowledged upon receipt by a destination media controller without waiting for achievement of persistence of write data associated with the write request. The tracker adds an identifier of the destination media controller to a tracking structure in response to the identifier not already being present in the tracking structure. The tracker sends a request to persist write operations to media controllers identified by the tracking structure.

公开(公告)号：US10664410B2

公开(公告)日：2020-05-26

申请号：US15735163

申请日：2015-06-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B Lesartre ,  Derek Alan Sherlock ,  Russ W Herrell

IPC: G06F12/00 ,  G06F12/1045 ,  G06F12/14 ,  G06F12/1027 ,  G06F13/16 ,  G06F9/50 ,  G06F21/62 ,  G06F9/30

Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.