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    Transmitting contents of an operation field to a media controller
    1.
    发明授权
    Transmitting contents of an operation field to a media controller 有权

    公开(公告)号：US10664410B2

    公开(公告)日：2020-05-26

    申请号：US15735163

    申请日：2015-06-18

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B Lesartre ,  Derek Alan Sherlock ,  Russ W Herrell

    IPC: G06F12/00 ,  G06F12/1045 ,  G06F12/14 ,  G06F12/1027 ,  G06F13/16 ,  G06F9/50 ,  G06F21/62 ,  G06F9/30

    Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.

    ELECTRONIC MODULES
    2.
    发明申请
    ELECTRONIC MODULES 审中-公开

    公开(公告)号：US20190035709A1

    公开(公告)日：2019-01-31

    申请号：US16072971

    申请日：2016-01-26

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B Lesartre

    IPC: H01L23/367 ,  H01L23/473 ,  H01L23/467 ,  H05K1/18

    Abstract: An example electronic device includes at least two electronic modules. Each electronic module includes a printed circuit board, heat generating components, and a heat spreader. The heat generating components are disposed on first and second surfaces of the printed circuit board. The heat spreader is disposed on the heat generating components opposite the printed circuit board. The heat spreader includes a base and fins extending from the base. The fins on a first side of a first of the at least two electronic modules extend toward a second of the at least two electronic modules. Fins on a second side of the second of the at least two electronic modules extend toward the first of the at least two electronic modules to interdigitate and share volumetric space between the printed circuit boards of the first and second of the at least two electronic modules.

    DATA MANAGEMENT ON MEMORY MODULES
    8.
    发明申请
    DATA MANAGEMENT ON MEMORY MODULES 审中-公开
    存储器模块的数据管理

    公开(公告)号：US20160202936A1

    公开(公告)日：2016-07-14

    申请号：US14912681

    申请日：2013-09-27

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B Lesartre ,  Andrew R Wheeler

    IPC: G06F3/06 ,  G06F12/10 ,  G06F12/12

    CPC classification number: G06F3/0685 ,  G06F3/0619 ,  G06F3/065 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1054 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/222 ,  G06F2212/60

    Abstract: Example implementations relate to managing data on a memory module. Data may be transferred between a first NVM and a second NVM on a memory module. The second NVM may have a higher memory capacity and a longer access latency than the first NVM. A mapping between a first address and a second address may be stored in an NVM on the memory module. The first address may refer to a location at which data is stored in the first NVM. The second address may refer to a location, in the second NVM, from which the data was copied.

    Abstract translation: 示例实现涉及管理存储器模块上的数据。 数据可以在存储器模块上的第一NVM和第二NVM之间传送。 第二NVM可能具有比第一NVM更高的存储容量和更长的访问延迟。 第一地址和第二地址之间的映射可以存储在存储器模块上的NVM中。 第一地址可以指数据存储在第一NVM中的位置。 第二地址可以指代数据被复制的第二NVM中的位置。

    External memory controller
    9.
    发明授权
    External memory controller 有权

    公开(公告)号：US11126372B2

    公开(公告)日：2021-09-21

    申请号：US16680254

    申请日：2019-11-11

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Russ W. Herrell ,  Gary Gostin ,  Gregg B Lesartre ,  Dale C. Morris

    IPC: G06F3/06

    Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.

    Iterative write sequence interrupt
    10.
    发明授权
    Iterative write sequence interrupt 审中-公开

    公开(公告)号：US10671291B2

    公开(公告)日：2020-06-02

    申请号：US15770753

    申请日：2015-11-17

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B Lesartre ,  Martin Foltin

    IPC: G06F3/06 ,  G06F13/24 ,  G06F13/16

    Abstract: Example implementations relate to memory read requests. For example, an implementation may include tracking progress of an iterative write sequence to write data to a memory element of a memory module. A received read request is detected to be addressed to a memory bank that includes the memory element undergoing the iterative write sequence. Based on the tracked progress, a time is determined to interrupt the iterative write sequence with insertion of the read request. The time aligns between operations of the iterative write sequence and data is returned within a predetermined read latency.

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