公开(公告)号：US20050176220A1

公开(公告)日：2005-08-11

申请号：US10988421

申请日：2004-11-12

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/205 ,  H01L21/22 ,  H01L21/285 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  C30B1/00 ,  H01L29/745

CPC分类号： H01L29/66628 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2205 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28562

摘要： A semiconductor device for efficiently forming a raised structure at a source/drain part of an MISFET having a gate electrode formed with a metal material by low temperature processes and a method therefore are provided. In a silicon buffer film formation process, a silicon buffer film is formed within a temperature range of 500° C. to 600° C. This silicon buffer film decreases the influence of impurities on a substrate surface. In a gas mixture supply process, a silicon-and-germanium mixed crystalline film is next formed within a temperature range of 500° C. to 600° C. By forming films at a low temperature of 500° C.-600° C., a raised structure at a source/drain part of an MIS field effect transistor having a gate electrode formed with metal can be formed.

摘要翻译： 提供一种用于通过低温工艺在具有由金属材料形成的栅电极的MISFET的源极/漏极部分处有效地形成凸起结构的半导体器件，因此提供了一种方法。 在硅缓冲膜形成工艺中，在500℃至600℃的温度范围内形成硅缓冲膜。该硅缓冲膜降低了杂质对基板表面的影响。 在气体混合物供给过程中，接下来在500℃至600℃的温度范围内形成硅 - 锗混合晶体膜。通过在500℃-600℃的低温下形成薄膜。 可以形成具有由金属形成的栅电极的MIS场效应晶体管的源极/漏极部分处的凸起结构。

公开(公告)号：US20050124105A1

公开(公告)日：2005-06-09

申请号：US11008770

申请日：2004-12-08

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/265 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52 ,  H01L29/78

CPC分类号： H01L29/665 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L21/28562 ,  H01L29/41783 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of manufacturing the same are provided. An underlayer film including nitrogen is formed on a predetermined region on an element isolation region, the predetermined region extending from a border of an active element forming region to the element isolation region side. Silicon or a mixed crystal of silicon or germanium is selectively formed on the underlayer film. Then the silicon or the mixed crystal of silicon and germanium is turned into a conductive film by ion implantation of a dopant or further making it to be a silicide. Subsequently, the conductive film formed on the element isolation region is electrically connected to an electrical wiring.

摘要翻译： 提供半导体器件及其制造方法。 在元件隔离区域上的预定区域上形成包括氮的下层膜，该预定区域从有源元件形成区域的边界延伸到元件隔离区域侧。 在下层膜上选择性地形成硅或硅或锗的混晶。 然后将硅或锗的混合晶体通过掺杂剂的离子注入转变为导电膜，或进一步使其成为硅化物。 随后，形成在元件隔离区上的导电膜电连接到电线。

公开(公告)号：US08736254B2

公开(公告)日：2014-05-27

申请号：US13116455

申请日：2011-05-26

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： G01P15/00

CPC分类号： G01P15/02 ,  G01P15/0802 ,  G01P15/125 ,  G01P15/18 ,  G01P2015/0831

摘要： A physical quantity sensor includes a first rocking body and a second rocking body. Each of the rocking bodies is supported on a substrate by a first supporting portion and a second supporting portion. The first rocking body is partitioned into a first region and a second region by a first axis (supporting axis) when viewed in plane, and the second rocking body is partitioned into a third region and a fourth region by a second axis (supporting axis) when viewed in plane. The mass of the second region is larger than the mass of the first region, and the mass of the third region is larger than the mass of the fourth region. An arranged direction of the first region and the second region is the same as an arranged direction of the third region and the fourth region.

摘要翻译： 物理量传感器包括第一摇摆体和第二摇摆体。 每个摇摆体通过第一支撑部分和第二支撑部分支撑在基底上。 当从平面观察时，第一摇摆体由第一轴线（支撑轴线）分隔成第一区域和第二区域，第二摇摆体通过第二轴线（支撑轴线）分隔成第三区域和第四区域， 当在飞机上看。 第二区域的质量大于第一区域的质量，第三区域的质量大于第四区域的质量。 第一区域和第二区域的排列方向与第三区域和第四区域的排列方向相同。

公开(公告)号：US07938506B2

公开(公告)日：2011-05-10

申请号：US12399340

申请日：2009-03-06

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： B41J2/135 ,  B41J2/045 ,  H01L41/22

CPC分类号： B41J2/161 ,  B41J2/14233 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1645 ,  B41J2/1646 ,  B41J2002/14241 ,  B41J2002/14491 ,  Y10T29/42

摘要： In a method for manufacturing an inkjet recording head which includes a pressure generation chamber supplied with ink fluid and a nozzle opening leading to the pressure generation chamber, the method includes: (a) forming a first trench which serves as the pressure generation chamber on a first surface of a first substrate; (b) forming a second trench which serves as the nozzle opening on a bottom surface of the first trench; (c) forming a sacrificial film on the first trench and the second trench; (d) forming a diaphragm on the sacrificial film as well as on the first surface of the first substrate; (e) forming a piezoelectric element on the diaphragm; (f) grinding a second surface of the first substrate so as to open a bottom surface of the second trench; (g) forming an opening which exposes the sacrificial film on the first surface of the first substrate; and (h) removing the sacrificial film through the opening.

摘要翻译： 在一种制造喷墨记录头的方法中，该喷墨记录头包括一个供应墨水流体的压力产生室和一个通向压力产生室的喷嘴开口，该方法包括：（a）在一个 第一基板的第一表面; （b）形成用作第一沟槽的底表面上的喷嘴开口的第二沟槽; （c）在所述第一沟槽和所述第二沟槽上形成牺牲膜; （d）在所述牺牲膜以及所述第一基板的所述第一表面上形成隔膜; （e）在隔膜上形成压电元件; （f）研磨第一基板的第二表面以打开第二沟槽的底表面; （g）形成在第一基板的第一表面上暴露牺牲膜的开口; 和（h）通过开口去除牺牲膜。

公开(公告)号：US07622359B2

公开(公告)日：2009-11-24

申请号：US12025093

申请日：2008-02-04

申请人： Juri Kato ,  Kei Kanemoto

发明人： Juri Kato ,  Kei Kanemoto

IPC分类号： H01L21/762

CPC分类号： H01L21/30604 ,  H01L21/7624

摘要： A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.

摘要翻译： 一种制造半导体器件的方法，包括：（a）在Si衬底上形成SiGe层; （b）在SiGe层上形成Si层; （c）在Si衬底的虚拟区域中形成由SiGe制成的虚拟图案; 和（d）湿法蚀刻除去Si层下形成的SiGe层。 在步骤（d）中，在完全去除SiGe层之前，蚀刻剂保持与伪图案接触，直至蚀刻结束。

公开(公告)号：US07524705B2

公开(公告)日：2009-04-28

申请号：US11494121

申请日：2006-07-26

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L21/00

CPC分类号： H01L21/7624 ,  H01L21/84

摘要： A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a predetermined region of a semiconductor base, forming a second semiconductor layer whose etching selective ratio is smaller than that of the first semiconductor layer on the first semiconductor layer, forming a support member to support the second semiconductor layer on the semiconductor base so as to cover the second semiconductor layer, forming an opening face in the support member to expose a portion of an edge of the first semiconductor layer, etching the first semiconductor layer through the opening face so as to form a cavity between the second semiconductor layer and the semiconductor base, cleaning between the second semiconductor layer and the semiconductor base through the opening face in a condition to remove a residue of the first semiconductor layer, and forming an insulating film in the cavity after cleaned.

摘要翻译： 一种制造半导体衬底的方法包括：在半导体基底的预定区域上形成第一半导体层，形成第二半导体层，其蚀刻选择比小于第一半导体层上的第一半导体层的蚀刻选择比，形成支撑构件 为了支撑半导体基底上的第二半导体层以覆盖第二半导体层，在支撑构件中形成开口面以暴露第一半导体层的边缘的一部分，通过开口面蚀刻第一半导体层，从而 为了在第二半导体层和半导体基底之间形成空腔，在去除第一半导体层的残留物的条件下，通过开口面清洁第二半导体层和半导体基底之间，以及在空腔中形成绝缘膜 清洗后。

公开(公告)号：US07507643B2

公开(公告)日：2009-03-24

申请号：US11605884

申请日：2006-11-29

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L27/12

CPC分类号： H01L29/66772 ,  H01L21/7621 ,  H01L29/78654

摘要： A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a semiconductor base; forming a second semiconductor layer having a lower etching selection ratio than the first semiconductor layer on the first semiconductor layer; removing a part of the second semiconductor layer and a part of the first semiconductor layer around an element region so as to form a recess for a support, the recess exposing the semiconductor base; forming a support forming layer on the semiconductor base so as to fill the recess and cover the second semiconductor layer; etching a part excluding the recess and the element region so as to form a support and an exposed face exposing a part of an end face of the first semiconductor layer and a part of an end face of the second semiconductor layer located under the support; etching the first semiconductor layer through the exposed face so as to form a cavity between the second semiconductor layer and the semiconductor base; forming a buried insulating layer in the cavity; and planarizing a top surface of the second semiconductor layer so as to remove a part of the support located on the second semiconductor layer. The recess is formed in a single-crystalline epitaxial region on the semiconductor base.

摘要翻译： 一种制造半导体衬底的方法包括在半导体基底上形成第一半导体层; 形成具有比所述第一半导体层上的所述第一半导体层更低的蚀刻选择比的第二半导体层; 在元件区域周围移除所述第二半导体层的一部分和所述第一半导体层的一部分，以形成用于支撑件的凹部，所述凹部暴露所述半导体基底; 在所述半导体基底上形成载体形成层，以填充所述凹部并覆盖所述第二半导体层; 蚀刻除了凹部和元件区域之外的部分，以形成支撑体和露出第一半导体层的端面的一部分和位于支撑体下方的第二半导体层的端面的一部分的暴露面; 通过所述暴露面蚀刻所述第一半导体层，以在所述第二半导体层和所述半导体基底之间形成空腔; 在空腔中形成掩埋绝缘层; 以及平坦化所述第二半导体层的顶表面，以便移除位于所述第二半导体层上的所述支撑体的一部分。 凹部形成在半导体基底上的单晶外延区域中。

公开(公告)号：US20080026511A1

公开(公告)日：2008-01-31

申请号：US11820320

申请日：2007-06-19

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L21/86

CPC分类号： H01L21/84

摘要： A method for manufacturing a semiconductor device includes: a) forming a first semiconductor layer which can be etched faster than a semiconductor substrate, on the semiconductor substrate including a first region that is arranged at a predetermined interval and is to be provided with a silicon on insulator (SOI) structure; b) forming a second semiconductor layer etched slower than the first semiconductor layer, on the first semiconductor layer; c) removing the first semiconductor layer and the second semiconductor layer from a second region which is adjacent to the first region via one line and disposed singly to each of the first region, so as to form a recess that exposes the semiconductor substrate, for a support; d) forming a support precursor layer made of insulating material on a region including at least the first region and the second region on the semiconductor substrate; e) etching and removing the support precursor layer except for a part thereof corresponding to the first region and corresponding to a part, including at least the one line, of a bottom part of the recess so as to form a support coupling the recess and the second semiconductor layer; f) etching a part of the first semiconductor layer and the second semiconductor layer by using the support as a mask to expose a first side section of the first semiconductor layer and the second semiconductor layer except for a second side section adjacent to the second region; g) etching and removing the first semiconductor layer selectively to the second semiconductor layer and the semiconductor substrate so as to form a cavity under the second semiconductor layer; h) thermally oxidizing the second semiconductor layer being an upper layer of the cavity and the semiconductor substrate being a lower layer of the cavity so as to form a buried insulating layer composed of a semiconductor oxide film in the cavity; and i) removing the support at least from the first region so as to expose the second semiconductor layer.

公开(公告)号：US20070262380A1

公开(公告)日：2007-11-15

申请号：US11796802

申请日：2007-04-30

申请人： Juri Kato ,  Kei Kanemoto

发明人： Juri Kato ,  Kei Kanemoto

IPC分类号： H01L27/12

CPC分类号： H01L21/823481 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor device comprises: a semiconductor substrate including a SOI region and a bulk region; a first element formed in the SOI region; a second element formed in the bulk region; a first element isolation layer including a trench structure; and a second element isolation layer including a LOCOS structure. The first element is separated from the second element by the first isolation layer and the second isolation layer.

摘要翻译： 半导体器件包括：包括SOI区域和体区域的半导体衬底; 形成在SOI区域中的第一元件; 形成在本体区域中的第二元件; 包括沟槽结构的第一元件隔离层; 以及包括LOCOS结构的第二元件隔离层。 第一元件通过第一隔离层和第二隔离层与第二元件分离。

公开(公告)号：US07294539B2

公开(公告)日：2007-11-13

申请号：US11393213

申请日：2006-03-29

申请人： Kei Kanemoto

发明人： Kei Kanemoto

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/02667 ,  H01L21/02639 ,  H01L21/2022 ,  H01L29/66795 ,  H01L29/785

摘要： A method of manufacturing a semiconductor device, includes: forming an insulating layer on a single crystal semiconductor substrate; forming a non-crystalline semiconductor layer on the insulating layer; forming an insulating film on the non-crystalline semiconductor layer; forming an opening section for exposing a part of a surface of the single crystal semiconductor substrate through the insulating film, the non-crystalline semiconductor layer and the insulating layer; forming a single crystal semiconductor layer embedded in the opening section so as to have contact with the non-crystalline semiconductor layer; removing the insulating film and the insulating layer while the single crystal semiconductor layer supporting the non-crystalline semiconductor layer above the single crystal semiconductor substrate; forming a single-crystallized semiconductor layer obtained by single-crystallizing the non-crystalline semiconductor layer using the single crystal semiconductor layer as a seed by providing a thermal treatment on the non-crystalline semiconductor layer from which the insulating film and the insulating layer are removed; filling a gap between the single-crystallized semiconductor layer and the single crystal semiconductor substrate with an embedded insulating layer; forming a gate electrode on the single-crystallized semiconductor layer; and forming in the single-crystallized semiconductor layer a source layer disposed on one side of the gate electrode and a drain layer disposed on the other side of the gate electrode.

摘要翻译： 一种制造半导体器件的方法包括：在单晶半导体衬底上形成绝缘层; 在所述绝缘层上形成非晶半导体层; 在非晶半导体层上形成绝缘膜; 形成用于通过所述绝缘膜，所述非晶半导体层和所述绝缘层使所述单晶半导体衬底的表面的一部分露出的开口部; 形成嵌入在所述开口部中以与所述非晶半导体层接触的单晶半导体层; 在单晶半导体衬底上支撑非晶半导体层的单晶半导体层的同时去除绝缘膜和绝缘层; 通过在除去绝缘膜和绝缘层的非晶半导体层上进行热处理，形成通过使用单晶半导体层作为种子将非晶半导体层单结晶而获得的单结晶半导体层 ; 用嵌入式绝缘层填充单晶半导体层和单晶半导体衬底之间的间隙; 在单结晶半导体层上形成栅电极; 以及在所述单结晶半导体层中形成设置在所述栅电极的一侧上的源极和设置在所述栅电极的另一侧的漏极层。