公开(公告)号：US08982609B2

公开(公告)日：2015-03-17

申请号：US13372099

申请日：2012-02-13

申请人： Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

发明人： Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

IPC分类号： G11C11/00

CPC分类号： G11C11/4094 ,  G11C11/419

摘要： A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.

摘要翻译： 存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。 读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。 读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。 读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

公开(公告)号：US08519444B2

公开(公告)日：2013-08-27

申请号：US12879447

申请日：2010-09-10

申请人： Annie Lum ,  Derek C. Tao ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Vineet Kumar Agrawal ,  Keun-Young Kim ,  Pyong Yun Cho

发明人： Annie Lum ,  Derek C. Tao ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Vineet Kumar Agrawal ,  Keun-Young Kim ,  Pyong Yun Cho

IPC分类号： H01L27/118

CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/088 ,  Y02P90/265

摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.

摘要翻译： 上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。 这种扩散区域的扩展可解决或减少LOD和边缘效应问题。 此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。 虚拟设备被禁用，其性能不重要。 因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

公开(公告)号：US08279684B2

公开(公告)日：2012-10-02

申请号：US12842189

申请日：2010-07-23

申请人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

发明人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C11/413

摘要： An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

摘要翻译： 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

公开(公告)号：US08488396B2

公开(公告)日：2013-07-16

申请号：US12700034

申请日：2010-02-04

申请人： Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Ji Liu

发明人： Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Ji Liu

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  G11C8/08

摘要： A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control.

摘要翻译： 静态随机存取存储器（SRAM）宏包括与第一电源电压不同的第一电源电压和第二电源电压。 预充电控制连接到第二电源电压。 预充电控制通过位线预充电耦合到位线。 至少一个电平移位器接收电平移位器输入。 电平移位器将具有比第二电源电压更接近于第一电源电压的电压电平的电平移位器输入转换为具有比第一电源电压更接近第二电源电压的电压电平的电平移位器输出。 电平移位器输出被提供给预充电控制。

公开(公告)号：US08451669B2

公开(公告)日：2013-05-28

申请号：US13443619

申请日：2012-04-10

申请人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

发明人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C5/14

摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

摘要翻译： 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

公开(公告)号：US20110158007A1

公开(公告)日：2011-06-30

申请号：US12708923

申请日：2010-02-19

申请人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

发明人： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/1048 ,  G11C5/14

摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

摘要翻译： 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

公开(公告)号：US08437210B2

公开(公告)日：2013-05-07

申请号：US13030722

申请日：2011-02-18

申请人： Ching-Wei Wu ,  Kuang Ting Chen ,  Cheng Hung Lee

发明人： Ching-Wei Wu ,  Kuang Ting Chen ,  Cheng Hung Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/065

摘要： A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.

摘要翻译： 电路包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管。 第一节点连接到第一PMOS晶体管和第一NMOS晶体管的栅极以及第二PMOS晶体管和第二NMOS晶体管的漏极。 第二节点连接到第二PMOS晶体管和第二NMOS晶体管的栅极以及第一PMOS晶体管和第一NMOS晶体管的漏极。 电路还包括具有连接到第一节点的第一电容的第一电容器; 以及具有连接到第二节点的第二电容的第二电容器。 第二电容大于第一电容。

公开(公告)号：US07750375B2

公开(公告)日：2010-07-06

申请号：US11529925

申请日：2006-09-30

申请人： Cheng Hung Lee

发明人： Cheng Hung Lee

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L27/105

摘要： This invention discloses a integrated circuit (IC) chip having a plurality of modular cells, the chip comprises a first modular cell having a first metal layer, which contains at least two power lines independent of each other; and a second modular cell, juxtaposed to the first modular cell, also having the first metal layer, which contains at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first modular cell do not extend into the second modular cell, and all the power lines on the first metal layer serving the second modular cell do not extend into the first modular cell.

摘要翻译： 本发明公开了一种具有多个模块单元的集成电路（IC）芯片，该芯片包括具有第一金属层的第一模块单元，该第一金属层包含彼此独立的至少两条电源线; 以及与第一模块单元并置的第二模块单元，其还具有第一金属层，该第一金属层包含彼此独立的至少两个电力线，其中用于第一模块单元的第一金属层上的所有电力线不延伸 并且服务于第二模块的第一金属层上的所有电力线不延伸到第一模块单元中。

公开(公告)号：US07613057B2

公开(公告)日：2009-11-03

申请号：US11732297

申请日：2007-04-03

申请人： Cheng Hung Lee

发明人： Cheng Hung Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C5/025

摘要： A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided.

摘要翻译： 一种电路和方法，用于为控制信号中的失真提供用于DRAM存储器的读出放大器，该读出放大器特别适用于将具有其他逻辑和存储器功能的DRAM存储器嵌入集成电路中。 为具有级联耦合的晶体管对的读出放大器中的差分感测锁存器提供感测使能电路，每个晶体管接收单独的控制信号。 单独的控制信号由具有延迟重叠的控制电路提供。 当分离的控制信号之间存在延迟的重叠时，启用差分感测。 DRAM存储单元的阵列耦合到多个读出放大器。 结合读出放大器的DRAM存储器可以与集成电路中的其它电路嵌入。 提供了提供控制信号和用读出放大器布置DRAM存储器的方法。

公开(公告)号：US20080080123A1

公开(公告)日：2008-04-03

申请号：US11529925

申请日：2006-09-30

申请人： Cheng Hung Lee

发明人： Cheng Hung Lee

IPC分类号： H01G9/00

CPC分类号： H01L27/0207 ,  H01L27/105

摘要： This invention discloses a integrated circuit (IC) chip having a plurality of modular cells, the chip comprises a first modular cell having a first metal layer, which contains at least two power lines independent of each other; and a second modular cell, juxtaposed to the first modular cell, also having the first metal layer, which contains at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first modular cell do not extend into the second modular cell, and all the power lines on the first metal layer serving the second modular cell do not extend into the first modular cell.

摘要翻译： 本发明公开了一种具有多个模块单元的集成电路（IC）芯片，该芯片包括具有第一金属层的第一模块单元，该第一金属层包含彼此独立的至少两条电源线; 以及与第一模块单元并置的第二模块单元，其还具有第一金属层，该第一金属层包含彼此独立的至少两个电力线，其中用于第一模块单元的第一金属层上的所有电力线不延伸 并且服务于第二模块的第一金属层上的所有电力线不延伸到第一模块单元中。