公开(公告)号：US20210193821A1

公开(公告)日：2021-06-24

申请号：US17112844

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L21/02 ,  H01L21/8238

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

公开(公告)号：US20180342524A1

公开(公告)日：2018-11-29

申请号：US15980604

申请日：2018-05-15

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/15 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2029/7858

Abstract: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device. The dielectric on the sidewalls of the first and third layers electrically isolates the source and drain regions from the gate contacting layer.