公开(公告)号：US10970076B2

公开(公告)日：2021-04-06

申请号：US16131376

申请日：2018-09-14

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Christopher J. Hughes ,  Bret Toll ,  Dan Baum ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F9/38 ,  G06F9/30 ,  G06F17/16

Abstract: Disclosed embodiments relate to systems and methods for performing instructions specifying ternary tile operations. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction specifying a ternary tile operation, and locations of destination and first, second, and third source matrices, each of the matrices having M rows by N columns; and execution circuitry to respond to the decoded instruction by, for each equal-sized group of K elements of the specified first, second, and third source matrices, generate K results by performing the ternary tile operation in parallel on K corresponding elements of the specified first, second, and third source matrices, and store each of the K results to a corresponding element of the specified destination matrix, wherein corresponding elements of the specified source and destination matrices occupy a same relative position within their associated matrix.

公开(公告)号：US12282773B2

公开(公告)日：2025-04-22

申请号：US18534012

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Menachem Adelman ,  Robert Valentine ,  Zeev Sperber ,  Mark J. Charney ,  Bret L. Toll ,  Rinat Rappoport ,  Jesus Corbal ,  Dan Baum ,  Alexander F. Heinecke ,  Elmoustapha Ould-Ahmed-Vall ,  Yuri Gebil ,  Raanan Sade

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US12260213B2

公开(公告)日：2025-03-25

申请号：US17548214

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Dan Baum ,  Zeev Sperber ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  Mark J. Charney ,  Barukh Ziv ,  Alexander Heinecke ,  Milind Girkar ,  Simon Rubanovich

IPC: G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

公开(公告)号：US12182571B2

公开(公告)日：2024-12-31

申请号：US18100194

申请日：2023-01-23

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Menachem Adelman ,  Milind B. Girkar ,  Zeev Sperber ,  Mark J. Charney ,  Bret L. Toll ,  Rinat Rappoport ,  Jesus Corbal ,  Stanislav Shwartsman ,  Dan Baum ,  Igor Yanover ,  Alexander F. Heinecke ,  Barukh Ziv ,  Elmoustapha Ould-Ahmed-Vall ,  Yuri Gebil ,  Raanan Sade

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

公开(公告)号：US20240354108A1

公开(公告)日：2024-10-24

申请号：US18478882

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Michael LeMay ,  David M. Durham ,  Joseph Cihula ,  Joseph Nuzman ,  Dan Baum ,  Jonathan Combs

IPC: G06F9/30

CPC classification number: G06F9/3016

Abstract: Techniques for implementing instructions and modified instruction encodings for checking tags and for interspersing islands of tags in line with bucketed data for locality by a processor are described. In an example, an apparatus includes decoder circuitry and execution circuitry. The decoder circuitry is to decode an instruction into a decoded instruction. The instruction has an opcode to indicate that the execution circuitry is to use metadata and instruction encodings to selectively perform a memory safety check. The execution circuitry is to execute the decoded instruction according to the opcode.

公开(公告)号：US12106100B2

公开(公告)日：2024-10-01

申请号：US16487421

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall ,  Dan Baum ,  Zeev Sperber ,  Jesus Corbal ,  Bret L. Toll ,  Raanan Sade ,  Igor Yanover ,  Yuri Gebil ,  Rinat Rappoport ,  Stanislav Shwartsman ,  Menachem Adelman ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US11886875B2

公开(公告)日：2024-01-30

申请号：US16232599

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Jonathan D. Pearce ,  Dan Baum ,  Guei-Yuan Lueh ,  Michael Espig ,  Christopher J. Hughes ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30038

Abstract: Disclosed embodiments relate to systems and methods for performing nibble-sized operations on matrix elements. In one example, a processor includes fetch circuitry to fetch an instruction, decode circuitry to decode the fetched instruction the fetched instruction having fields to specify an opcode and locations of first source, second source, and destination matrices, the opcode to indicate the processor is to, for each pair of corresponding elements of the first and second source matrices, logically partition each element into nibble-sized partitions, perform an operation indicated by the instruction on each partition, and store execution results to a corresponding nibble-sized partition of a corresponding element of the destination matrix. The exemplary processor includes execution circuitry to execute the decoded instruction as per the opcode.

公开(公告)号：US11748103B2

公开(公告)日：2023-09-05

申请号：US17672253

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30178 ,  G06F9/3013 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3802

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US11579880B2

公开(公告)日：2023-02-14

申请号：US17240882

申请日：2021-04-26

Applicant: INTEL CORPORATION

Inventor： Bret Toll ,  Christopher J. Hughes ,  Dan Baum ,  Elmoustapha Ould-Ahmed-Vall ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F9/30

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

公开(公告)号：US11567765B2

公开(公告)日：2023-01-31

申请号：US16487766

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Menachem Adelman ,  Milind B. Girkar ,  Zeev Sperber ,  Mark J. Charney ,  Bret L. Toll ,  Rinat Rappoport ,  Jesus Corbal ,  Stanislav Shwartsman ,  Dan Baum ,  Igor Yanover ,  Alexander F. Heinecke ,  Barukh Ziv ,  Elmoustapha Ould-Ahmed-Vall ,  Yuri Gebil

IPC: G06F9/38 ,  G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.