公开(公告)号：US20190205236A1

公开(公告)日：2019-07-04

申请号：US15859016

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Jonathan Combs ,  Jason Brandt

IPC: G06F11/34 ,  G06F9/54 ,  G06F11/30

Abstract: Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.

公开(公告)号：US11907712B2

公开(公告)日：2024-02-20

申请号：US17033649

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Thomas Madaelil ,  Jonathan Combs ,  Vikash Agarwal

IPC: G06F9/30 ,  G06F9/22 ,  G06F9/38

CPC classification number: G06F9/223 ,  G06F9/382 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/3844

Abstract: Systems, methods, and apparatuses relating to circuitry to implement out-of-order access to a shared microcode sequencer by a clustered decode pipeline are described. In one embodiment, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, a fetch circuit to fetch a first block of instructions and send the first block of instructions to the first decode cluster for decoding, and fetch a second block of instructions younger in program order than the first block of instructions and send the second block of instructions to the second decode cluster for decoding, a microcode sequencer comprising a memory that stores a plurality of micro-operations, and an arbitration circuit to arbitrate access by the first decode cluster and the second decode cluster to a shared read port of the memory, wherein the arbitration circuit is to allow the second decode cluster decoding the second block of instructions access to the shared read port of the memory instead of the first decode cluster decoding the first block of instructions when an instruction of the second block of instructions has a number of corresponding micro-operations in the microcode sequencer below an arbitration threshold.

公开(公告)号：US20230195593A1

公开(公告)日：2023-06-22

申请号：US17556751

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Claudia Romo ,  Jonathan Combs ,  Beeman Strong

IPC: G06F11/34 ,  G06F11/30 ,  G06F11/07

CPC classification number: G06F11/3466 ,  G06F11/3409 ,  G06F11/3072 ,  G06F11/076

Abstract: In one embodiment, an apparatus includes: at least one core to execute instructions; and a plurality of fixed counters coupled to the at least one core, the plurality of fixed counters to count events during execution on the at least one core, at least some of the plurality of fixed counters to count event information of a highest level of a hierarchical performance monitoring organization. Other embodiments are described and claimed.

公开(公告)号：US20230099989A1

公开(公告)日：2023-03-30

申请号：US17484969

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sundararajan Ramakrishnan ,  Jonathan Combs ,  Martin J. Licht ,  Santhosh Srinath

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/07

Abstract: Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described. In one example, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, and a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster, wherein the toggle point control circuit is to: determine a location in an instruction stream as a candidate toggle point to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster, track a number of times a characteristic of multiple previous decodes of the instruction stream is present for the location, and cause insertion of a toggle point at the location, based on the number of times, to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster.

公开(公告)号：US12229034B2

公开(公告)日：2025-02-18

申请号：US16748382

申请日：2020-01-21

Applicant: Intel Corporation

Inventor： Jonathan Combs ,  Jason Brandt

IPC: G06F3/00 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34

Abstract: Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.

公开(公告)号：US20230185572A1

公开(公告)日：2023-06-15

申请号：US17549192

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Martin Licht ,  Jonathan Combs

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3802 ,  G06F9/3818

Abstract: An embodiment of an integrated circuit may comprise a core and an instruction decoder communicatively coupled to the core to decode one or more instructions for execution by the core, where the instruction decoder includes two or more decode clusters in a parallel arrangement, and circuitry to offline a decode cluster of the two or more decode clusters. Other embodiments are disclosed and claimed.

公开(公告)号：US10579492B2

公开(公告)日：2020-03-03

申请号：US15859016

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Jonathan Combs ,  Jason Brandt

IPC: G06F3/00 ,  G06F11/34 ,  G06F11/30 ,  G06F9/54

Abstract: Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.

公开(公告)号：US20150089143A1

公开(公告)日：2015-03-26

申请号：US14557474

申请日：2014-12-02

Applicant: Intel Corporation

Inventor： Martin Licht ,  Jonathan Combs ,  Andrew Huang

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F9/3806 ,  G06F9/3814 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Abstract translation: 这里描述了用于响应于基于历史的使用模式来禁用缓存存储器的方式的方法和装置。 方式预测逻辑是跟踪高速缓存访​​问的方式，并确定是否要禁用某些方式的访问以节省功率，这是基于具有表示预测错过的逻辑状态的功率信号的方式。 与方式计数访问相关联的一个或多个计数器，其中当所述一个或多个计数器之一达到饱和值时，功率信号被设置为表示预测的未命中的逻辑状态。 控制逻辑根据访问方式来调整与一些或多个计数器相关联的方式。

公开(公告)号：US20230401067A1

公开(公告)日：2023-12-14

申请号：US17840029

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Mathew Lowes ,  Martin Licht ,  Jonathan Combs

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3016

Abstract: In one embodiment, an apparatus comprises: a branch prediction circuit to predict whether a branch is to be taken; a fetch circuit, in a single fetch cycle, to send a first portion of a fetch region of instructions to a first decode cluster and send a second portion of the fetch region to the second decode cluster; the first decode cluster comprising a first plurality of decode circuits to decode one or more instructions in the first portion of the fetch region; and the second decode cluster comprising a second plurality of decode circuits to decode one or more other instructions in the second portion of the fetch region. Other embodiments are described and claimed.

公开(公告)号：US20220318020A1

公开(公告)日：2022-10-06

申请号：US17214693

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Mathew Lowes ,  Jonathan Combs ,  Martin Licht

IPC: G06F9/38

Abstract: Techniques and mechanisms for providing branch prediction information to facilitate instruction decoding by a processor. In an embodiment, entries of a branch prediction table (BTB) each identify, for a corresponding instruction, whether a prediction based on the instruction (if any) is eligible to be communicated, with another prediction, in a single fetch cycle. A branch prediction unit of the processor determines a linear address of a fetch region which is under consideration, and performs a search of the BTB based on the linear address. A result of the search is evaluated to detect for any hit entry which indicates a double prediction eligibility. In another embodiment, where it is determined that double prediction eligibility is indicated for an earliest one the instructions represented by the hit entries, multiple predictions are communicated in a single fetch cycle.