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    TRANSPARENT SANITIZATION FOR SYNCHRONIZATION MESSAGES IN TIME SENSITIVE NETWORKING
    31.
    发明公开
    TRANSPARENT SANITIZATION FOR SYNCHRONIZATION MESSAGES IN TIME SENSITIVE NETWORKING 审中-公开

    公开(公告)号：US20240223585A1

    公开(公告)日：2024-07-04

    申请号：US18090682

    申请日：2022-12-29

    Applicant: Intel Corporation

    Inventor： Christopher Gutierrez ,  Vuk Lesi ,  Marcio Juliato ,  Manoj Sastry ,  Shabbir Ahmed

    IPC: H04L9/40 ,  H04J3/06

    CPC classification number: H04L63/1425 ,  H04J3/0667 ,  H04L63/1416

    Abstract: Techniques include receiving a message with time information at an ingress queue for an ingress interface of an intrusion detection system (IDS), the IDS to monitor a network node of a time-synchronized network (TSN), generating an entrance timestamp for the message, the entrance timestamp to comprise a time value representing when the message is received at the ingress queue of the ingress interface of the IDS, inspecting the message for indications of a security attack by the IDS, generating an exit timestamp for the message, the exit timestamp to comprise a time value representing when the message is received at an egress queue of an egress interface of the IDS, and generating an inspection time interval associated with the IDS, the inspection time interval to represent a time interval between the entrance timestamp and the exit timestamp for the message while transiting the IDS. Other embodiments are described and claimed.

    Processor hardware and instructions for lattice based cryptography
    36.
    发明授权
    Processor hardware and instructions for lattice based cryptography 有权

    公开(公告)号：US11792005B2

    公开(公告)日：2023-10-17

    申请号：US17699830

    申请日：2022-03-21

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Manoj Sastry

    IPC: H04L9/40 ,  H04L9/30

    CPC classification number: H04L9/3093 ,  H04L2209/12

    Abstract: A method comprises fetching, by fetch circuitry, an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers, decoding, by decode circuitry, the decoded butterfly instruction to generate a decoded butterfly instruction, and executing, by execution circuitry, the decoded butterfly instruction to retrieve operands representing a first input polynomial-coefficient from the first source, a second input polynomial-coefficient from the second source, and a primitive nth root of unity from the third source, perform, in an atomic fashion, a butterfly operation to generate a first output polynomial-coefficient and a second output polynomial-coefficient, and store the first output coefficient and the second output coefficient in a register file accessible to the execution circuitry.

    Robust state synchronization for stateful hash-based signatures
    37.
    发明授权
    Robust state synchronization for stateful hash-based signatures 有权

    公开(公告)号：US11750403B2

    公开(公告)日：2023-09-05

    申请号：US17816148

    申请日：2022-07-29

    Applicant: Intel Corporation

    Inventor： Manoj Sastry ,  Rafael Misoczki ,  Jordan Loney ,  David M. Wheeler

    IPC: G06F21/72 ,  H04L9/32

    CPC classification number: H04L9/3247 ,  G06F21/72 ,  H04L9/3236

    Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.

    POLYNOMIAL MULTIPLICATION FOR SIDE-CHANNEL PROTECTION IN CRYPTOGRAPHY
    39.
    发明申请
    POLYNOMIAL MULTIPLICATION FOR SIDE-CHANNEL PROTECTION IN CRYPTOGRAPHY 有权

    公开(公告)号：US20230091951A1

    公开(公告)日：2023-03-23

    申请号：US17478579

    申请日：2021-09-17

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Manoj Sastry

    IPC: H04L9/30 ,  H04L9/08 ,  G06F7/53 ,  G06F7/487

    Abstract: Polynomial multiplication for side-channel protection in cryptography is described. An example of a apparatus includes one or more processors to process data; a memory to store data; and polynomial multiplier circuitry to multiply a first polynomial by a second polynomial, the first polynomial and the second polynomial each including a plurality of coefficients, the polynomial multiplier circuitry including a set of multiplier circuitry, wherein the polynomial multiplier circuitry is to select a first coefficient of the first polynomial for processing, and multiply the first coefficient of the first polynomial by all of the plurality of coefficients of the second polynomial in parallel using the set of multiplier circuits.

    Accelerating multiple post-quantum cryptograhy key encapsulation mechanisms
    40.
    发明授权
    Accelerating multiple post-quantum cryptograhy key encapsulation mechanisms 有权

    公开(公告)号：US11569994B2

    公开(公告)日：2023-01-31

    申请号：US17356972

    申请日：2021-06-24

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Andrew Reinders ,  Manoj Sastry

    IPC: H04L9/30 ,  H04L9/06 ,  H04L9/14

    Abstract: An accelerator includes polynomial multiplier circuitry including at least one modulus multiplier operating according to a mode. The at least one modulus multiplier include a multiplier to multiply two polynomial coefficients to generate a multiplication result, a power of two reducer to reduce the multiplication result to a reduced multiplication result when the mode is a power of two mode, and a prime modulus reducer to reduce the multiplication result to the reduced multiplication result when the mode is a prime modulus mode.

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