-
公开(公告)号：US09037627B2
公开(公告)日：2015-05-19
申请号：US13763598
申请日：2013-02-08
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
CPC classification number: G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
Abstract translation: 一种用于在处理器中包括用于对打包或未打包的数据执行逻辑比较和分支支持操作的指令的方法和装置。 在一个实施例中，指令解码逻辑解码用于执行单元对包括逻辑比较的打包数据元素进行操作的指令。 包括128位打包数据寄存器的寄存器文件存储打包的单精度浮点数（SPFP）和压缩整数数据元素。 逻辑比较可以包括SPFP数据元素的比较和整数数据元素的比较，并且设置至少一个位以指示结果。 基于这些比较，采取分支支持行动。 这种分支支持动作可以包括设置至少一个比特，响应于分支指令又可以由分支单元利用该比特。 或者，分支支持动作可以包括分支到指示的目标代码位置。
-
32.发明授权公开(公告)号：US11294670B2
公开(公告)日：2022-04-05
申请号：US16366155
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Christopher J. Hughes , Jonathan D. Pearce , Guei-Yuan Lueh , ElMoustapha Ould-Ahmed-Vall , Jorge E. Parra , Prasoonkumar Surti , Krishna N. Vinod , Ronen Zohar
Abstract: Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.
-
公开(公告)号：US11249761B2
公开(公告)日：2022-02-15
申请号：US16934003
申请日：2020-07-20
Applicant: Intel Corporation
Inventor： Dan Baum , Michael Espig , James Guilford , Wajdi K. Feghali , Raanan Sade , Christopher J. Hughes , Robert Valentine , Bret Toll , Elmoustapha Ould-Ahmed-Vall , Mark J. Charney , Vinodh Gopal , Ronen Zohar , Alexander F. Heinecke
Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.
-
公开(公告)号：US10817297B2
公开(公告)日：2020-10-27
申请号：US16370922
申请日：2019-03-30
Applicant: Intel Corporation
Inventor： Christopher J. Hughes , ElMoustapha Ould-Ahmed-Vall , Jorge E. Parra , Prasoonkumar Surti , Krishna N. Vinod , Ronen Zohar
Abstract: Methods and apparatus for vector-matrix comparison are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry decodes an instruction, where operands of the instruction specifies an output location to store output results, a vector of data element values, and a matrix of data element values. The execution circuitry executes the decoded instruction. The execution includes to map each of the data element values of the vector to one of consecutive rows of the matrix; for each data element value of the vector, to compare that data element value of the vector with data element values in a respective row of the matrix and obtain data element match results. The execution further includes to store the output results based on the data element match results, where each output result maps to a respective data element column position and indicates a vector match result.
-
Patent Agency Ranking
公开(公告)号：US10572251B2
公开(公告)日：2020-02-25
申请号：US16184994
申请日：2018-11-08
Applicant: INTEL CORPORATION
Inventor： Rajiv Kapoor , Ronen Zohar , Mark J. Buxton , Zeev Sperber , Koby Gottlieb
IPC: G06F9/30 , G06F7/02 , G06F9/38 , G06F12/0875
Abstract: A method and apparatus for including in processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
-
公开(公告)号：US20170322805A1
公开(公告)日：2017-11-09
申请号：US15661219
申请日：2017-07-27
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
-
公开(公告)号：US09286267B2
公开(公告)日：2016-03-15
申请号：US13793648
申请日：2013-03-11
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
CPC classification number: G06F9/30014 , G06F7/49947 , G06F9/30025 , G06F9/30036 , G06F9/30167 , G06F9/30181 , G06F9/30185 , G06F17/10
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
-
公开(公告)号：US09268565B2
公开(公告)日：2016-02-23
申请号：US14684412
申请日：2015-04-12
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
CPC classification number: G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
-
公开(公告)号：US09170813B2
公开(公告)日：2015-10-27
申请号：US13763596
申请日：2013-02-08
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
CPC classification number: G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
-
-
-
-
-
-
-
-
Search Results
39
records
(took 0.023 seconds)
