公开(公告)号：US11892950B2

公开(公告)日：2024-02-06

申请号：US17865666

申请日：2022-07-15

申请人： Intel Corporation

发明人： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, Jr. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC分类号： G06F12/084 ,  G06F12/0862 ,  G06T1/20 ,  G06T1/60

CPC分类号： G06F12/0862 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/602 ,  G06F2212/608

摘要： Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US20210357618A1

公开(公告)日：2021-11-18

申请号：US17221283

申请日：2021-04-02

申请人： Intel Corporation

发明人： Radhakrishnan Venkataraman ,  James M. Holland ,  Sayan Lahiri ,  Pattabhiraman K ,  Kamal Sinha ,  Chandrasekaran Sakthivel ,  Daniel Pohl ,  Vivek Tiwari ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Devan Burke

IPC分类号： G06K9/00 ,  G09G5/10 ,  G09G5/391 ,  G06F3/01 ,  G06F3/147 ,  G09G5/00 ,  G09G5/393 ,  G09G5/36

摘要： Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

公开(公告)号：US10929129B2

公开(公告)日：2021-02-23

申请号：US16458040

申请日：2019-06-29

申请人： Intel Corporation

发明人： ElMoustapha Ould-Ahmed-Vall

IPC分类号： G06F9/30 ,  G06F13/40

摘要： Apparatus and method for Modifying Addresses, Data, or Program Code Associated With Offloaded Instructions. One embodiment of a processor comprises: a plurality of cores; an interconnect coupling the plurality of cores; and offload circuitry to transfer work from a first core of the plurality of cores to a second core of the plurality of cores without operating system (OS) intervention, the work comprising a plurality of instructions; the second core comprising a translator to translate information associated with a first instruction of the plurality of instructions from a first format usable on the first core to a second format usable on the second core; fetch, decode, and execution circuitry of the second core to fetch, decode, and/or execute the first instruction using the second format.

公开(公告)号：US10424097B2

公开(公告)日：2019-09-24

申请号：US15476990

申请日：2017-04-01

申请人： Intel Corporation

发明人： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  ElMoustapha Ould-Ahmed-Vall ,  James M. Holland

IPC分类号： G09G5/00 ,  G06T11/60 ,  G06T9/00 ,  H04N19/503 ,  H04N19/124 ,  H04N19/17 ,  H04N19/167 ,  H04N19/436

摘要： An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.

公开(公告)号：US20180286115A1

公开(公告)日：2018-10-04

申请号：US15477016

申请日：2017-04-01

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

IPC分类号： G06T15/80 ,  G06T5/20 ,  G06F9/50 ,  G06T1/20

CPC分类号： G06T15/80 ,  G06F9/50 ,  G06F9/5011 ,  G06T1/20 ,  G06T5/20

摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

公开(公告)号：US20180284872A1

公开(公告)日：2018-10-04

申请号：US15477010

申请日：2017-04-01

申请人： Intel Corporation

发明人： Travis T. Schluessler ,  Joydeep Ray ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Kamal Sinha ,  James M. Holland ,  Pattabhiraman K. ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Carson Brownlee ,  Vivek Tiwari ,  Kai Xiao ,  Jefferson Amstutz ,  Deepak S. Vembar ,  Ankur N. Shah ,  ElMoustapha Ould-Ahmed-Vall

IPC分类号： G06F1/32 ,  G06T1/20 ,  G06T7/13

摘要： An embodiment may include an application processor, persistent storage media coupled to the application processor, and a graphics subsystem coupled to the application processor. The system may further include any of a performance analyzer to analyze a performance of the graphics subsystem to provide performance analysis information, a content-based depth analyzer to analyze content to provide content-based depth analysis information, a focus analyzer to analyze a focus area to provide focus analysis information, an edge analyzer to provide edge analysis information, a frame analyzer to provide frame analysis information, and/or a variance analyzer to analyze respective amounts of variance for the frame. The system may further include a workload adjuster to adjust a workload of the graphics subsystem based on the analysis information. Other embodiments are disclosed and claimed.

公开(公告)号：US12066975B2

公开(公告)日：2024-08-20

申请号：US17429291

申请日：2020-03-14

申请人： Intel Corporation

发明人： Altug Koker ,  Lakshminarayanan Striramassarma ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Sean Coleman ,  Varghese George ,  K Pattabhiraman ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  Joydeep Ray ,  S Jayakrishna P ,  Prasoonkumar Surti

IPC分类号： G06F12/00 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

公开(公告)号：US11494868B2

公开(公告)日：2022-11-08

申请号：US17180235

申请日：2021-02-19

申请人： Intel Corporation

发明人： Joydeep Ray ,  Ankur N. Shah ,  Abhishek R. Appu ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall ,  Atsuo Kuwahara ,  Travis T. Schluessler ,  Linda L. Hurd ,  Josh B. Mastronarde ,  Vasanth Ranganathan

IPC分类号： G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06F9/30 ,  G06F9/38

摘要： An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.

公开(公告)号：US20220197653A1

公开(公告)日：2022-06-23

申请号：US17131741

申请日：2020-12-22

申请人： Intel Corporation

发明人： ElMoustapha Ould-Ahmed-Vall

IPC分类号： G06F9/30 ,  G06F9/38

摘要： Techniques for extracting strided data elements from three source two dimensional (2D) arrays are described. A processor of an aspect includes a decoder circuitry to decode an instruction having an opcode. The instruction may indicate a first source 2D array, a second source 2D array, and a third source 2D array. Execution circuitry is coupled with the decoder circuitry. The execution circuitry is to execute the decoded instruction to select, for each one dimensional (1D) array of data elements in a first dimension, of each of the first, second, and third source 2D arrays, only a plurality of data elements at data element positions separated by a stride of three. The execution circuitry is also to store the selected plurality of data elements in a result 2D array in a destination storage location. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20220197652A1

公开(公告)日：2022-06-23

申请号：US17131733

申请日：2020-12-22

申请人： Intel Corporation

发明人： ElMoustapha Ould-Ahmed-Vall

IPC分类号： G06F9/30 ,  G06F7/32 ,  G06F17/16

摘要： Techniques for merging two source two dimensional (2D) arrays are described. A processor of an aspect includes a decoder circuitry to decode an instruction having an opcode. The instruction may indicate a first source 2D array and a second source 2D array. Execution circuitry is coupled with the decoder circuitry. The execution circuitry is to execute the decoded instruction to merge a plurality of portions of the first 2D array, and a plurality of portions of the second 2D array, to generate a result 2D array. The instruction does not indicate a plurality of values to specify the plurality of portions of the first 2D array and the plurality of portions of the second 2D array. The execution circuitry is also to store the result 2D array in a destination storage location. Other processors, methods, systems, and instructions are disclosed.