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    POST QUANTUM PUBLIC KEY SIGNATURE OPERATION FOR RECONFIGURABLE CIRCUIT DEVICES
    35.
    发明申请
    POST QUANTUM PUBLIC KEY SIGNATURE OPERATION FOR RECONFIGURABLE CIRCUIT DEVICES 有权

    公开(公告)号：US20220108039A1

    公开(公告)日：2022-04-07

    申请号：US17551961

    申请日：2021-12-15

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Rafael Misoczki ,  Santosh Ghosh ,  Raghavan Kumar ,  Manoj Sastry ,  Andrew H. Reinders

    IPC: G06F21/72 ,  G06F21/76 ,  H04L9/32 ,  H04L9/08

    Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.

    Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator
    37.
    发明授权
    Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator 有权

    公开(公告)号：US10928847B2

    公开(公告)日：2021-02-23

    申请号：US16147652

    申请日：2018-09-29

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Sudhir Satpathy

    IPC: G06F9/02 ,  G06F1/06

    Abstract: Methods and apparatuses relating to a hashing accelerator having a frequency scaled message scheduler data path circuit are described. In one embodiment, a hardware accelerator includes a message digest data path circuit comprising a first message digest circuit to output a second state vector, at a first clock rate, based on a first state vector and an output from a first switch, and a second message digest circuit to output a third state vector, at the first clock rate, based on the second state vector and an output from a second switch; a message scheduler data path circuit comprising at least one first message scheduler circuit to output an element into a second message vector, at a second clock rate that is slower than the first clock rate, based on a plurality of elements of a first message vector, and at least one second message scheduler circuit to output an element into a fourth message vector, at the second clock rate that is slower than the first clock rate, based on a plurality of elements of a third message vector; and a controller to switch the first switch at the second clock rate between sourcing a first element of the first message vector and a first element of the third message vector as the output from the first switch, and switch the second switch at the second clock rate between sourcing a second element of the first message vector and a second element of the third message vector as the output from the second switch.

    Hardware accelerators and methods for high-performance authenticated encryption
    38.
    发明授权
    Hardware accelerators and methods for high-performance authenticated encryption 有权

    公开(公告)号：US10705842B2

    公开(公告)日：2020-07-07

    申请号：US15943654

    申请日：2018-04-02

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Sudhir Satpathy ,  Vinodh Gopal

    IPC: G06F9/302 ,  G06F9/305 ,  G06F9/315 ,  H04L9/00 ,  H04L9/18 ,  G06F9/30 ,  G06F9/38 ,  H04L9/06

    Abstract: Methods and apparatuses relating to high-performance authenticated encryption are described. A hardware accelerator may include a vector register to store an input vector of a round of an encryption operation; a circuit including a first data path including a first modular adder coupled to a first input from the vector register and a second input from the vector register, and a second modular adder coupled to the first modular adder and a second data path from the vector register, and the second data path including a first logical XOR circuit coupled to the second input and a third data path from the vector register, a first rotate circuit coupled to the first logical XOR circuit, a second logical XOR circuit coupled to the first rotate circuit and the third data path, and a second rotate circuit coupled to the second logical XOR circuit; and a control circuit to cause the first modular adder and the second modular adder of the first data path and the first logical XOR circuit, the second logical XOR circuit, the first rotate circuit, and the second rotate circuit of the second data path to perform a portion of the round according to one or more control values, and store a first result from the first data path for the portion and a second result from the second data path for the portion into the vector register.

    Variable format, variable sparsity matrix multiplication instruction
    39.
    发明授权
    Variable format, variable sparsity matrix multiplication instruction 有权

    公开(公告)号：US10599429B2

    公开(公告)日：2020-03-24

    申请号：US16003545

    申请日：2018-06-08

    Applicant: Intel Corporation

    Inventor： Mark A. Anders ,  Himanshu Kaul ,  Sanu Mathew

    IPC: G06F9/30 ,  G06F17/16 ,  G06N20/00 ,  G06N3/063

    Abstract: Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.

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