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    Security-Guided Adjustment of Time-Sync Frequency in Time Synchronized Networking
    34.
    发明公开
    Security-Guided Adjustment of Time-Sync Frequency in Time Synchronized Networking 审中-公开

    公开(公告)号：US20240171593A1

    公开(公告)日：2024-05-23

    申请号：US17990091

    申请日：2022-11-18

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Vuk Lesi ,  Manoj Sastry

    IPC: H04L9/40 ,  H04J3/06

    CPC classification number: H04L63/1416 ,  H04J3/0658 ,  H04L63/1466

    Abstract: Techniques include an apparatus to retrieve a first parameter for the IDS to monitor a device for a time-synchronized network. The first parameter may represent a number of messages the IDS needs to analyze in order to detect a security attack. The messages may comprise time information to synchronize a clock for a device to a network time for a time-synchronized network. The processor circuitry may retrieve a second parameter for a time sensitive application. The second parameter may represent a defined amount of time error tolerated by the time sensitive application, and determine a third parameter for the IDS based on the first and second parameters. The third parameter may represent a defined frequency to receive a number of messages with time information in order to detect the security attack on the device within a defined time interval. Other embodiments are described and claimed.

    CLOCK MANAGER REDUNDANCY FOR TIME SYNCHRONIZED NETWORKS
    35.
    发明公开
    CLOCK MANAGER REDUNDANCY FOR TIME SYNCHRONIZED NETWORKS 审中-公开

    公开(公告)号：US20240143020A1

    公开(公告)日：2024-05-02

    申请号：US17974113

    申请日：2022-10-26

    Applicant: Intel Corporation

    Inventor： Vuk Lesi ,  Christopher Gutierrez ,  Shabbir Ahmed ,  Marcio Juliato ,  Manoj Sastry

    IPC: G06F1/12 ,  G06F1/10

    CPC classification number: G06F1/12 ,  G06F1/10 ,  G06F1/08

    Abstract: An apparatus for clock manager redundancy comprises a clock circuitry to manage a clock for a device; a first processing circuitry coupled to the clock circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network; a hardened execution environment coupled to the clock circuitry and the first processing circuitry, the hardened execution environment to comprise: a detector to monitor the clock manager and generate an alert when the detector identifies abnormal behavior of the clock manager; and a second processing circuitry to execute instructions to perform operations for a redundant clock manager, the redundant clock manager to take over operations for the clock manager in response to the alert from the detector. Other embodiments are described and claimed.

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