公开(公告)号：US09899313B2

公开(公告)日：2018-02-20

申请号：US15207077

申请日：2016-07-11

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jean Audet ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Brian R. Sundlof

IPC: H01L23/52 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19103

Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.

公开(公告)号：US20160172288A1

公开(公告)日：2016-06-16

申请号：US14571352

申请日：2014-12-16

Applicant: International Business Machines Corporation

Inventor： Jean Audet ,  Benjamin V. Fasano ,  Shidong Li

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L21/486 ,  H01L21/0274 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.