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公开(公告)号：US20130284495A1
公开(公告)日：2013-10-31
申请号：US13932070
申请日：2013-07-01
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Alexandre Blander , Peter J. Brofman , Donald W. Henderson , Gareth G. Hougham , Hsichang Liu , Eric D. Perfecto , Srinivasa S.N. Reddy , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof , Julien Sylvestre , Renee L. Weisman
CPC classification number: H01B1/02 , B23K35/0244 , B23K35/262 , B23K35/36 , B23K35/3602 , B82Y30/00 , C22C13/00 , H01B13/00 , H01L23/49866 , H01L2924/0002 , H05K3/3436 , H05K3/3463 , H05K2201/0209 , H05K2201/0257 , Y10T29/49117 , H01L2924/00
Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
Abstract translation: 在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。 惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。 在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。 添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。
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公开(公告)号：US11171102B2
公开(公告)日：2021-11-09
申请号：US16250456
申请日：2019-01-17
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof
IPC: H01L23/00
Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
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公开(公告)号：US09263363B2
公开(公告)日：2016-02-16
申请号：US14047290
申请日：2013-10-07
Applicant: International Business Machines Corporation
Inventor： Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
IPC: H01L23/04 , H01L23/373 , B82Y30/00 , H01L23/40
CPC classification number: H01L23/3733 , B82Y30/00 , H01L23/373 , H01L23/3736 , H01L23/40 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , Y10S977/788 , Y10T156/10 , Y10T428/24994 , H01L2224/0401
Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.
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4.发明申请Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive 有权导热材料的自定向微板作为热膏或粘合剂中的组分公开(公告)号：US20140038362A1
公开(公告)日：2014-02-06
申请号：US14047290
申请日：2013-10-07
Applicant: International Business Machines Corporation
Inventor： Gareth Hougham , Paul A. Lauro , Brian R. Sundlof , Jeffrey D. Gelorme
IPC: H01L23/373 , H01L23/40
CPC classification number: H01L23/3733 , B82Y30/00 , H01L23/373 , H01L23/3736 , H01L23/40 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , Y10S977/788 , Y10T156/10 , Y10T428/24994 , H01L2224/0401
Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.
Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。
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公开(公告)号：US10403590B2
公开(公告)日：2019-09-03
申请号：US15445058
申请日：2017-02-28
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof
IPC: H01L23/00
Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20180053717A1
公开(公告)日：2018-02-22
申请号：US15796770
申请日：2017-10-28
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof
IPC: H01L23/522 , H01L23/00
CPC classification number: H01L23/5223 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/50 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/18 , H01L2224/13101 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2924/15311 , H01L2924/16152 , H01L2924/19103 , H01L2924/19107 , H01L2924/014 , H01L2924/00014 , H01L2924/00
Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.
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公开(公告)号：US11244917B2
公开(公告)日：2022-02-08
申请号：US16502648
申请日：2019-07-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof
IPC: H01L23/00
Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
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公开(公告)号：US10396051B2
公开(公告)日：2019-08-27
申请号：US15405431
申请日：2017-01-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof
IPC: H01L23/00
Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
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公开(公告)号：US10224274B2
公开(公告)日：2019-03-05
申请号：US15796782
申请日：2017-10-28
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof
IPC: H01L23/00 , H01L23/50 , H01L25/18 , H01L23/367 , H01L23/498 , H01L23/522
Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.
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公开(公告)号：US10224273B2
公开(公告)日：2019-03-05
申请号：US15796770
申请日：2017-10-28
Applicant: International Business Machines Corporation
Inventor： Charles L. Arvin , Jean Audet , Brian W. Quinlan , Charles L. Reynolds , Brian R. Sundlof
IPC: H01L23/00 , H01L23/50 , H01L25/18 , H01L23/367 , H01L23/498 , H01L23/522
Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.
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