公开(公告)号：US10916253B2

公开(公告)日：2021-02-09

申请号：US16173939

申请日：2018-10-29

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu

IPC: G10L15/30 ,  G10L15/22 ,  G06Q10/10 ,  G10L15/26

Abstract: Method, system, and apparatus for storing conversation data of a conversation onto a blockchain network, the conversation data comprising terms of an agreement, the method comprising: receiving audio data of a conversation between two or more participants; creating a transcript of at least some of the audio data; accessing a database comprising a plurality of words or phrases. The method, system, and apparatus are also for obtaining, from the database, predefined one or more words associated with a predefined topic; searching the transcript for the predefined one or more words; filtering the transcript based on the predefined one or more words; and storing the conversation data onto a first block of a blockchain stored on the blockchain network, wherein the conversation data comprises the filtered transcript.

公开(公告)号：US10796949B2

公开(公告)日：2020-10-06

申请号：US16165251

申请日：2018-10-19

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu ,  Naftali Lustig ,  Matthew Angyal

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.

公开(公告)号：US20200258770A1

公开(公告)日：2020-08-13

申请号：US16858484

申请日：2020-04-24

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu ,  Naftali Lustig ,  Matthew Angyal

IPC: H01L21/768 ,  H01L23/522

Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.

公开(公告)号：US10559564B2

公开(公告)日：2020-02-11

申请号：US16052526

申请日：2018-08-01

Applicant: International Business Machines Corporation

Inventor： Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/51 ,  H01L29/165 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/82 ,  H01L21/8238 ,  H01L21/3105

Abstract: A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed only upon the sidewalls of the fins.

公开(公告)号：US10552758B2

公开(公告)日：2020-02-04

申请号：US16374505

申请日：2019-04-03

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Werner A. Rausch ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: G06N99/00 ,  H01L27/18 ,  G06N10/00 ,  H01L39/24 ,  H01G4/008 ,  H01L39/02 ,  H01L39/22 ,  H01L49/02

Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.

公开(公告)号：US10529908B2

公开(公告)日：2020-01-07

申请号：US16267463

申请日：2019-02-05

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L21/8242 ,  H01L39/02 ,  G06N10/00 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L39/22 ,  H01L39/24 ,  H03K19/195

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

公开(公告)号：US10445651B2

公开(公告)日：2019-10-15

申请号：US16020902

申请日：2018-06-27

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Werner A. Rausch ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: G06N99/00 ,  H01L27/18 ,  G06N10/00 ,  H01G4/008 ,  H01L39/24 ,  H01L39/02 ,  H01L39/22

Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.

公开(公告)号：US20180342510A1

公开(公告)日：2018-11-29

申请号：US16051820

申请日：2018-08-01

Applicant: International Business Machines Corporation

Inventor： Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/165 ,  H01L29/16 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/82 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/8238

Abstract: A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

公开(公告)号：US20180301448A1

公开(公告)日：2018-10-18

申请号：US15799247

申请日：2017-10-31

Applicant: International Business Machines Corporation

Inventor： Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/82 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/165 ,  H01L29/51 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

公开(公告)号：US10068184B1

公开(公告)日：2018-09-04

申请号：US15795763

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Werner A. Rausch ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: G06N99/00 ,  H01L27/18 ,  H01L39/22 ,  H01L39/24 ,  H01G4/008 ,  H01L39/02

Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.