公开(公告)号：US11783105B2

公开(公告)日：2023-10-10

申请号：US17207030

申请日：2021-03-19

Applicant: Imagination Technologies Limited

Inventor： Simon Gaulter ,  Thomas Ferrere ,  Faizan Nazar ,  Sam Elliott

IPC: G06F30/30 ,  G06F30/33

CPC classification number: G06F30/33

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

公开(公告)号：US20230297747A1

公开(公告)日：2023-09-21

申请号：US18201070

申请日：2023-05-23

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F30/33 ,  G06F30/3323 ,  G06F30/337 ,  G01R31/3183

CPC classification number: G06F30/33 ,  G06F30/3323 ,  G06F30/337 ,  G01R31/318314 ,  G06F2119/16

Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

公开(公告)号：US20230221924A1

公开(公告)日：2023-07-13

申请号：US18119355

申请日：2023-03-09

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F7/485

CPC classification number: G06F7/485

Abstract: Circuits and associated methods for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A−B) of the two numbers include calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|−|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A−B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|−|B|), and the sign of each floating-point number.

公开(公告)号：US20230031551A1

公开(公告)日：2023-02-02

申请号：US17854927

申请日：2022-06-30

Applicant: Imagination Technologies Limited

Inventor： Thomas Rose ,  Sam Elliott

IPC: G06F7/74 ,  G06F7/523 ,  G06F7/535 ,  G06F30/392

Abstract: A fixed logic circuit configured to determine one or more of the most significant bits of the multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2m−1, and m is a positive integer, the fixed logic circuit comprising: division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation: ⌊ 2 i ⁢ x q ⌋ where i is the minimum positive value which satisfies: 2 i ( 2 i ⁢ mod ⁢ a ) > a * ( 2 m - 1 ) + 1 ⁢ q = ⌊ 2 i a ⌋ and output logic configured to provide the one or more most significant bits of the result of the division operation as the respective one or more most significant bits of the multiplication operation a*x.

公开(公告)号：US20220147677A1

公开(公告)日：2022-05-12

申请号：US17501666

申请日：2021-10-14

Applicant: Imagination Technologies Limited

Inventor： Rachel Edmonds ,  Sam Elliott

IPC: G06F30/3323

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k+1 when the value of the kth difference is not predetermined.

公开(公告)号：US11294634B2

公开(公告)日：2022-04-05

申请号：US16548359

申请日：2019-08-22

Applicant: Imagination Technologies Limited

Inventor： Jonas Källén ,  Sam Elliott

IPC: G06F7/556 ,  G06F7/72 ,  G06F7/487

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b] mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0: m] mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ┌log2 M┐; and more than M−2u of the subset of modulo units are arranged at the maximal delay of ┌log2 M┐, where 2u is the power of 2 immediately smaller than M.

公开(公告)号：US20220004690A1

公开(公告)日：2022-01-06

申请号：US17478739

申请日：2021-09-17

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F30/3323 ,  G01R31/3183

Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.

公开(公告)号：US11126771B2

公开(公告)日：2021-09-21

申请号：US16372138

申请日：2019-04-01

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F30/3323 ,  G06F30/367 ,  G06F30/398 ,  G06F30/3308 ,  G06F30/323 ,  G01R31/3183

Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.

公开(公告)号：US20210042086A1

公开(公告)日：2021-02-11

申请号：US16932923

申请日：2020-07-20

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F7/485

Abstract: Circuits and associated methods for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A-B) of the two numbers include calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|−|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A-B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|−|B|), and the sign of each floating-point number.

公开(公告)号：US20190311074A1

公开(公告)日：2019-10-10

申请号：US16372138

申请日：2019-04-01

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F17/50 ,  G01R31/3183

Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.