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    VERIFICATION OF HARDWARE DESIGN FOR DATA TRANSFORMATION COMPONENT
    2.
    发明公开
    VERIFICATION OF HARDWARE DESIGN FOR DATA TRANSFORMATION COMPONENT 审中-公开

    公开(公告)号：US20230297747A1

    公开(公告)日：2023-09-21

    申请号：US18201070

    申请日：2023-05-23

    申请人： Imagination Technologies Limited

    发明人： Sam Elliott

    IPC分类号： G06F30/33 ,  G06F30/3323 ,  G06F30/337 ,  G01R31/3183

    CPC分类号： G06F30/33 ,  G06F30/3323 ,  G06F30/337 ,  G01R31/318314 ,  G06F2119/16

    摘要： A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

    VERIFICATION OF HARDWARE DESIGN FOR DATA TRANSFORMATION COMPONENT
    5.
    发明公开
    VERIFICATION OF HARDWARE DESIGN FOR DATA TRANSFORMATION COMPONENT 审中-公开

    公开(公告)号：US20240320407A1

    公开(公告)日：2024-09-26

    申请号：US18675048

    申请日：2024-05-27

    申请人： Imagination Technologies Limited

    发明人： Sam Elliott

    IPC分类号： G06F30/33 ,  G01R31/3183 ,  G06F30/3308 ,  G06F30/3323 ,  G06F30/337 ,  G06F111/12 ,  G06F115/02 ,  G06F119/16

    CPC分类号： G06F30/33 ,  G01R31/318314 ,  G06F30/3323 ,  G06F30/337 ,  G06F30/3308 ,  G06F2111/12 ,  G06F2115/02 ,  G06F2119/16

    摘要： A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

    Attribute-Point-Based Timing Constraint Formal Verification
    8.
    发明公开
    Attribute-Point-Based Timing Constraint Formal Verification 审中-公开

    公开(公告)号：US20230205958A1

    公开(公告)日：2023-06-29

    申请号：US18176717

    申请日：2023-03-01

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chao-Chun Lo ,  Boh-Yi Huang ,  Chih-yuan Stephen Yu

    IPC分类号： G06F30/33

    CPC分类号： G06F30/33 ,  G06F2119/16

    摘要： Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).

    Verification of hardware design for data transformation component
    9.
    发明授权
    Verification of hardware design for data transformation component 有权

    公开(公告)号：US11995386B2

    公开(公告)日：2024-05-28

    申请号：US18201070

    申请日：2023-05-23

    申请人： Imagination Technologies Limited

    发明人： Sam Elliott

    IPC分类号： G06F30/30 ,  G01R31/3183 ,  G06F30/33 ,  G06F30/3323 ,  G06F30/337 ,  G06F30/3308 ,  G06F111/12 ,  G06F115/02 ,  G06F119/16

    CPC分类号： G06F30/33 ,  G01R31/318314 ,  G06F30/3323 ,  G06F30/337 ,  G06F30/3308 ,  G06F2111/12 ,  G06F2115/02 ,  G06F2119/16

    摘要： A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

    Attribute-Point-Based Timing Constraint Formal Verification
    10.
    发明公开
    Attribute-Point-Based Timing Constraint Formal Verification 审中-公开

    公开(公告)号：US20240160820A1

    公开(公告)日：2024-05-16

    申请号：US18418546

    申请日：2024-01-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chao-Chun Lo ,  Boh-Yi Huang ,  Chih-yuan Stephen Yu

    IPC分类号： G06F30/33

    CPC分类号： G06F30/33 ,  G06F2119/16

    摘要： Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).