Abstract:
Circuitry and methods are described for digital signal demodulation. In a configurable receiver, a method includes receiving a radio frequency signal at the configurable receiver, operating the configurable receiver in a first mode, the first mode including providing the radio frequency signal to an amplitude detection circuit to determine an amplitude, providing the radio frequency signal to a phase detection circuit to determine a phase, and providing the amplitude and phase to a coordinate rotation digital computer (CORDIC) logic circuit, and operating the configurable receiver in a low power mode upon receiving an indication to selectively disable the amplitude detection circuit, the low power mode including providing the radio frequency signal to the phase detection circuit to determine the phase, and providing the phase and a predetermined constant value in lieu of the amplitude to the CORDIC logic circuit.
Abstract:
A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.
Abstract:
A method of generating inphase and quadrature signals from a polar receiver providing a phase derivative signal and an envelope magnitude signal comprising receiving an estimated phase derivative signal; generating an estimated phase signal; mapping the estimated phase signal to an angular value; converting the estimated phase signal to an inphase signal and a quadrature signal based on the angular value; and, providing the inphase signal and quadrature signal to a demodulation circuit.
Abstract:
Single-bit transmitter modulator having a digital pulse shaping filter configured to shape data pulses of an inphase signal and quadrature signal; an upsampling filter configured to increase the sample rate of the inphase signal and quadrature signal; a sigma-delta modulator providing a one-bit inphase output signal and a one-bit quadrature output signal; an inphase low-order analog low pass filter coupling the one-bit inphase output signal to an inphase channel input of a quadrature modulator, and a quadrature low-order analog low pass filter coupling the one-bit quadrature output signal to a quadrature channel input of a quadrature modulator; and, wherein the quadrature modulator is connected to a carrier signal generator and is configured to generate an inphase and quadrature modulated carrier.
Abstract:
A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.
Abstract:
A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.
Abstract:
A configurable array having a plurality of antenna elements arranged in at least four adjacent groups of array elements on a panel array, the first group of elements having an inter-element spacing based on a transmit signal wavelength, a second group of elements having an inter-element spacing based on a receive signal wavelength, and a third and fourth group of elements having an inter-element spacing based on a wavelength between the transmit signal wavelength and the receive signal wavelength.
Abstract:
Selectively enabling an amplitude processing circuit and a phase processing circuit of a wireless station's polar receiver with respect to reception of a beacon signal. Such systems and methods may include sequentially demodulating symbols of the received beacon signal using at least the phase processing circuit to detect a traffic indication signal value in a data payload portion of the received beacon signal. Upon detecting a condition indicating no data traffic for the wireless station, the phase processing circuit may be turned off. The polar receiver may demodulate symbols of the received beacon signal and upon detecting a beacon preamble symbol sequence, shut off the amplitude processing circuit and set the amplitude to a fixed value. The phase processing circuit in conjunction with the fixed amplitude value may be used to demodulate symbols of the beacon signal.
Abstract:
Systems and methods are provided for aligning amplitude and phase signals in a polar receiver. A receiver generates digital amplitude and phase signals representing the amplitude and phase of a modulated input signal. At least one of the digital signals is filtered using a fractional delay filter with a variable delay. The delay of the fractional delay filter is adjusted to align the amplitude and phase signals. In some embodiments, an error vector magnitude is determined by comparing in-phase and quadrature values of the signal with values corresponding to a constellation point, and the delay is adjusted based on the error vector magnitude. The fractional delay filter may be a finite impulse response filter with coefficients stored in a lookup table that correspond to different delays.
Abstract:
A predistortion circuit receives an input polar signal to be transmitted, including an input amplitude signal and an input phase signal. The input polar signal is predistorted using at least one predistortion parameter selected from a lookup table. A phase-and-amplitude modulated radio-frequency signal is generated corresponding to the predistorted polar signal. A copy of the generated radio-frequency signal is provided to a polar receiver. The polar receiver is operated to generate, from the copy of the radio-frequency signal and without information relating to the generated transmit signal, a feedback polar signal including a feedback amplitude signal and a feedback phase signal. The feedback polar signal is compared to the input polar signal, the lookup table is updated in response to the comparison.