公开(公告)号：US20210272231A1

公开(公告)日：2021-09-02

申请号：US17200581

申请日：2021-03-12

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  David Puffer ,  Abhishek R. Appu ,  Stephen Junkins

IPC: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06T1/60

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：US20210191872A1

公开(公告)日：2021-06-24

申请号：US17191473

申请日：2021-03-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210056033A1

公开(公告)日：2021-02-25

申请号：US17026264

申请日：2020-09-20

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200341766A1

公开(公告)日：2020-10-29

申请号：US16397217

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Bryan R. White ,  Ankur N. Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

IPC: G06F9/30 ,  G06F12/0831 ,  G06F12/0837 ,  G06F9/48 ,  G06F9/54 ,  G06F9/38

Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.

公开(公告)号：US20200258191A1

公开(公告)日：2020-08-13

申请号：US16791514

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/60 ,  G06T1/20

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US10706493B2

公开(公告)日：2020-07-07

申请号：US15858583

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Yunbiao Lin ,  Changliang Wang ,  Satyanantha Ramagopal Musunuri ,  David Puffer ,  David J. Cowperthwaite ,  Bryan R White ,  Balaji Vembu

IPC: G06T1/20 ,  G06T1/60 ,  G06F3/14 ,  G06F9/451 ,  G09G5/00 ,  G09G5/36

Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.

公开(公告)号：US20190304052A1

公开(公告)日：2019-10-03

申请号：US16441499

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  David Puffer ,  Abhishek R. Appu ,  Stephen Junkins

IPC: G06T1/20 ,  G06T1/60 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：US10282812B2

公开(公告)日：2019-05-07

申请号：US15482808

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06T1/20

Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.

公开(公告)号：US20180089091A1

公开(公告)日：2018-03-29

申请号：US15275912

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Tomas G. Akenine-Moller ,  Prasoonkumar Surti ,  Altug Koker ,  David Puffer ,  Jim K. Nilsson

IPC: G06F12/0875 ,  G06T1/60 ,  G06T15/00 ,  G06T1/20

Abstract: Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.

公开(公告)号：US20230298129A1

公开(公告)日：2023-09-21

申请号：US17849165

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  David Cowperthwaite ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/1009 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/1009 ,  G06T1/20 ,  G06F2212/302

Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.