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    Apparatus and method for scalable error detection and reporting
    2.
    发明授权
    Apparatus and method for scalable error detection and reporting 有权

    公开(公告)号：US11704181B2

    公开(公告)日：2023-07-18

    申请号：US17849356

    申请日：2022-06-24

    Applicant: Intel Corporation

    Inventor： Balaji Vembu ,  Bryan White ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Mahesh Natu

    IPC: G06F11/00 ,  G06F11/07

    CPC classification number: G06F11/0769 ,  G06F11/0784 ,  G06F11/0787

    Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

    MEMORY MAPPED VIRTUAL DOORBELL MECHANISM
    7.
    发明申请
    MEMORY MAPPED VIRTUAL DOORBELL MECHANISM 审中-公开

    公开(公告)号：US20200341766A1

    公开(公告)日：2020-10-29

    申请号：US16397217

    申请日：2019-04-29

    Applicant: Intel Corporation

    Inventor： Bryan R. White ,  Ankur N. Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

    IPC: G06F9/30 ,  G06F12/0831 ,  G06F12/0837 ,  G06F9/48 ,  G06F9/54 ,  G06F9/38

    Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.

    System coherency in a distributed graphics processor hierarchy
    9.
    发明授权
    System coherency in a distributed graphics processor hierarchy 有权
    分布式图形处理器层次结构中的系统一致性

    公开(公告)号：US09436972B2

    公开(公告)日：2016-09-06

    申请号：US14227525

    申请日：2014-03-27

    Applicant: Intel Corporation

    Inventor： Altug Koker ,  Aditya Navale

    IPC: G09G5/36 ,  G06T1/00 ,  G06F15/00 ,  G06T1/60 ,  G06F12/08

    CPC classification number: G06T1/60 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0831 ,  G06F2212/1024 ,  G06F2212/455

    Abstract: Methods and systems may provide for executing, by a physically distributed set of compute slices, a plurality of work items. Additionally, the coherency of one or more memory lines associated with the plurality of work items may be maintained, by a cache fabric, across a graphics processor, a system memory and one or more host processors. In one example, a plurality of crossbar nodes track the one or more memory lines, wherein the coherency of the one or more memory lines is maintained across a plurality of level one (L1) caches and a physically distributed cache structure. Each L1 cache may be dedicated to an execution block of a compute slice and each crossbar node may be dedicated to a compute slice.

    Abstract translation: 方法和系统可以提供通过物理分布的计算片段来执行多个工作项目。 此外，与多个工作项相关联的一个或多个存储器线的一致性可以由缓存结构跨图形处理器，系统存储器和一个或多个主机处理器来维护。 在一个示例中，多个交叉开关节点跟踪一个或多个存储器线，其中一个或多个存储器线的一致性被保持在多个一级（L1）高速缓存和物理分布的高速缓存结构上。 每个L1高速缓存可以专用于计算片的执行块，并且每个交叉节点可以专用于计算片。

    Dynamic cache and memory allocation for memory subsystems
    10.
    发明授权
    Dynamic cache and memory allocation for memory subsystems 有权
    内存子系统的动态缓存和内存分配

    公开(公告)号：US09323684B2

    公开(公告)日：2016-04-26

    申请号：US14221491

    申请日：2014-03-21

    Applicant: Intel Corporation

    Inventor： Altug Koker ,  Aditya Navale

    IPC: G09G5/36 ,  G06T1/60 ,  G06F12/08

    CPC classification number: G06F12/0871 ,  G06F12/0875 ,  G09G2360/121 ,  Y02D10/13

    Abstract: Technologies are presented that allow a portion of a cache to be used as a front memory when there is dynamic need based on system demand. A computing system may include at least one processor, a memory controlled by a controller and communicatively coupled with the at least one processor, a cache communicatively coupled with the at least one processor and the memory, and mapping logic communicatively coupled with the at least one processor, the memory, and the cache. The mapping logic may map a portion of the cache to a portion of the memory, wherein the portion of the cache is to be used by the at least one processor as a local memory, and wherein the mapping is dynamic based on system demand and managed by the controller in a physical address domain.

    Abstract translation: 当存在基于系统需求的动态需求时，提供允许一部分高速缓存用作前端存储器的技术。 计算系统可以包括至少一个处理器，由控制器控制并与所述至少一个处理器通信耦合的存储器，与所述至少一个处理器和所述存储器通信地耦合的高速缓存器，以及与所述至少一个处理器通信耦合的映射逻辑 处理器，内存和缓存。 所述映射逻辑可将所述高速缓存的一部分映射到所述存储器的一部分，其中所述高速缓存的所述部分将由所述至少一个处理器用作本地存储器，并且其中所述映射基于系统需求而动态地被管理 由控制器在物理地址域中。

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