公开(公告)号：US20230185603A1

公开(公告)日：2023-06-15

申请号：US17551166

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Saurabh Gayen ,  Philip Lantz ,  Narayan Ranganathan ,  Dhananjay Joshi ,  Rajesh Sankaran ,  Utkarsh Kakaiya

IPC: G06F9/48 ,  G06Q30/02

CPC classification number: G06F9/4881 ,  G06Q30/0283

Abstract: Methods and apparatus relating to dynamic capability discovery and enforcement for accelerators and devices in multi-tenant systems are described. In an embodiment, a hardware accelerator device advertises one or more available operations and/or capabilities of the hardware accelerator device to one or more tenants. Logic circuitry controls access to the one or more available operations and/or capabilities of the one or more work queues on a per-tenant basis. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230032236A1

公开(公告)日：2023-02-02

申请号：US17875198

申请日：2022-07-27

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Philip R. Lantz ,  Narayan Ranganathan ,  Saurabh Gayen ,  Sanjay Kumar ,  Nikhil Rao ,  Dhananjay A. Joshi ,  Hai Ming Khor ,  Utkarsh Y. Kakaiya

IPC: G06F3/06

Abstract: Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry provides high-performance data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.

公开(公告)号：US11290392B2

公开(公告)日：2022-03-29

申请号：US15620376

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Mohan J. Kumar ,  Donald L. Faw ,  Susanne M. Balle ,  Narayan Ranganathan

IPC: H04L12/927 ,  H04L29/08 ,  H04L12/933 ,  H04L12/865 ,  H04L47/80 ,  H04L67/00 ,  H04L49/109 ,  H04L67/1097 ,  H04L47/6275

Abstract: Technologies for pooling accelerators over fabric are disclosed. In the illustrative embodiment, an application may access an accelerator device over an application programming interface (API) and the API can access an accelerator device that is either local or a remote accelerator device that is located on a remote accelerator sled over a network fabric. The API may employ a send queue and a receive queue to send and receive command capsules to and from the accelerator sled.

公开(公告)号：US11093277B2

公开(公告)日：2021-08-17

申请号：US16913265

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US11029659B2

公开(公告)日：2021-06-08

申请号：US16314401

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Nicolas A. Salhuana ,  Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Narayan Ranganathan

IPC: G06F13/38 ,  G05B19/042 ,  H03K19/17732 ,  G06F8/41 ,  H03K19/17728

Abstract: In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.

公开(公告)号：US20200341810A1

公开(公告)日：2020-10-29

申请号：US16392822

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Narayan Ranganathan ,  Sujoy Sen ,  Joseph Grecco ,  Slawomir Putyrski

IPC: G06F9/50

Abstract: Technologies for providing an accelerator device discovery service include a device having circuitry configured to obtain, from a discovery service, availability data indicative of a set of accelerator devices available to assist in the execution of a workload. The circuitry is also configured to select, as a function of the availability data, one or more target accelerator devices to assist in the execution of the workload, and execute the workload with the one or more target accelerator devices.

公开(公告)号：US20200218684A1

公开(公告)日：2020-07-09

申请号：US16242928

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Narayan Ranganathan

IPC: G06F13/40 ,  G06F11/20 ,  G06F3/06 ,  G06F15/173 ,  G06F9/455 ,  H04L29/06 ,  H04L29/08

Abstract: Technologies for accessing pooled accelerator resources over a network fabric are disclosed. In disclosed embodiments, an application hosted by a computing platform accesses remote accelerator resources over a network fabric using protocol multipathing mechanisms. A communication session is established with the remote accelerator resources. The communication session comprises at least two connections. The at least two connections at least include a first connection having or utilizing a first transport layer and a second connection having or utilizing a second transport layer that is different than the first transport layer. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US10430267B2

公开(公告)日：2019-10-01

申请号：US15206853

申请日：2016-07-11

Applicant: INTEL CORPORATION

Inventor： Ashok Raj ,  Narayan Ranganathan

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/14

Abstract: A computing system can include a machine check counter (MCC) including a current value. The current value indicates a system reboot resetting hardware of the computing system. The machine check counter includes a model specific register including a counter indicating the current value, the current value to be incremented upon the system reboot.

公开(公告)号：US10320710B2

公开(公告)日：2019-06-11

申请号：US14865162

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Charles A. Giefer ,  Raj K. Ramanujan ,  Robert G. Blankenship ,  Narayan Ranganathan

IPC: H04L12/931 ,  H04L5/00 ,  H04L12/26 ,  H04L12/18

Abstract: Methods, apparatus, and systems for reliable replication mechanisms based on active-passive HFI protocols build on top of non-reliable multicast fabric implementations. Under a first hardware-based scheme, a reliable replication mechanism is (primarily) implemented via Host Fabric Interfaces (HFIs) coupled to (or integrated in) nodes coupled to a non-reliable fabric. Under this approach, the HFIs take an active role in ensuring reliable delivery of multicast messages to each of multiple target nodes. Under a second hybrid software/hardware scheme, software running on nodes is responsible for determining whether target nodes have confirmed delivery of multicast messages and sending retry messages for cases in which delivery is not acknowledged within a timeout period. At the same time, the HFIs on the target nodes are responsible for generating reply messages containing acknowledgements rather than software running on the target nodes.

公开(公告)号：US08751864B2

公开(公告)日：2014-06-10

申请号：US13848830

申请日：2013-03-22

Applicant: Intel Corporation

Inventor： Robert C. Swanson ,  Mahesh S. Natu ,  Rahul Khanna ,  Murugasamy K. Nachimuthu ,  Sarathy Jayakumar ,  Anil S. Keshavamurthy ,  Narayan Ranganathan

IPC: G06F11/00

CPC classification number: G06F11/203 ,  G06F11/1666 ,  G06F11/20

Abstract: In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明提供了处理在高可用性系统中的存储器迁移操作期间发生的错误的能力。 此外，可以使用一种方法来将存储在存储器的非镜像存储器区域中的存储器页面动态重映射到镜像存储器区域。 该动态重新映射可以响应于确定存储器页已经被访问多于阈值次数，指示页面上的信息的关键性。 描述和要求保护其他实施例。