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公开(公告)号:US12191987B2
公开(公告)日:2025-01-07
申请号:US18388461
申请日:2023-11-09
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Susanne M. Balle , Rahul Khanna , Sujoy Sen , Karthik Kumar
IPC: H04L43/08 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G06F15/16 , G06F16/174 , G06F16/901 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04B10/25 , H04L41/14 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/356 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/00 , H05K7/14 , B25J15/00 , B65G1/04 , G05D23/19 , G05D23/20 , G06F9/50 , G06F11/14 , G06F11/34 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F13/42 , G06F15/80 , G06Q10/06 , G06Q10/0631 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/00 , G11C5/06 , H04J14/00 , H04L9/06 , H04L9/14 , H04L9/32 , H04L12/28 , H04L41/02 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/70 , H04L47/765 , H04L47/78 , H04L47/80 , H04L47/83 , H04L49/15 , H04L49/55 , H04L61/00 , H04L67/00 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/51 , H04Q1/04 , H04W4/02 , H04W4/80 , H05K1/02 , H05K1/18 , H05K5/02 , H05K7/20 , H05K13/04
Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
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公开(公告)号:US12155538B2
公开(公告)日:2024-11-26
申请号:US18210478
申请日:2023-06-15
Applicant: Intel Corporation
Inventor: Mrittika Ganguli , Muthuvel M. I , Ananth S. Narayan , Jaideep Moses , Andrew J. Herdrich , Rahul Khanna
IPC: H04L41/50 , H04L41/14 , H04L41/5009 , H04L41/5025
Abstract: In accordance with some embodiments, a cloud service provider may operate a data center in a way that dynamically reallocates resources across nodes within the data center based on both utilization and service level agreements. In other words, the allocation of resources may be adjusted dynamically based on current conditions. The current conditions in the data center may be a function of the nature of all the current workloads. Instead of simply managing the workloads in a way to increase overall execution efficiency, the data center instead may manage the workload to achieve quality of service requirements for particular workloads according to service level agreements.
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公开(公告)号:US12130688B2
公开(公告)日:2024-10-29
申请号:US17133226
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Rahul Khanna , Xin Kang , Ali Taha , James Tschanz , William Zand , Robert Kwasnick
IPC: G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/50
CPC classification number: G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/5094
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.
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公开(公告)号:US20240143410A1
公开(公告)日:2024-05-02
申请号:US18405679
申请日:2024-01-05
Applicant: Intel Corporation
Inventor: Susanne M. Balle , Francesc Guim Bernat , Slawomir Putyrski , Joe Grecco , Henry Mitchel , Evan Custodio , Rahul Khanna , Sujoy Sen
IPC: G06F9/50 , G06F3/06 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/38 , G06F9/4401 , G06F9/455 , G06F9/48 , G06F9/54 , G06F11/07 , G06F11/30 , G06F11/34 , G06F12/02 , G06F12/06 , G06F13/16 , G06F16/174 , G06F21/57 , G06F21/62 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/00 , H01R13/453 , H01R13/631 , H03K19/173 , H03M7/30 , H03M7/40 , H03M7/42 , H04L9/08 , H04L12/28 , H04L12/46 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/14
CPC classification number: G06F9/505 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0641 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/45533 , G06F9/4843 , G06F9/4881 , G06F9/5005 , G06F9/5038 , G06F9/5044 , G06F9/5083 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3079 , G06F11/3409 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/453 , H01R13/4536 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/1452 , H05K7/1487 , H05K7/1491 , H04L47/78
Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.
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公开(公告)号:US11856493B2
公开(公告)日:2023-12-26
申请号:US17480910
申请日:2021-09-21
Applicant: Intel Corporation
Inventor: Christopher R. Carlson , Rahul Khanna , Greeshma Pisharody
IPC: H04W4/70 , G06F1/3287 , H04W52/02 , G06F1/3234 , G06Q10/0833 , H04W4/38 , G06Q10/083 , G06Q10/087 , H02J50/10 , H04L67/10 , H04W4/029 , H04W4/80 , G06F21/35 , H04W4/46
CPC classification number: H04W4/70 , G06F1/325 , G06F1/3287 , G06Q10/083 , G06Q10/087 , G06Q10/0833 , H04W4/38 , H04W52/0229 , G06F21/35 , H02J50/10 , H04L67/10 , H04W4/029 , H04W4/46 , H04W4/80
Abstract: Lost, misplaced, incorrectly delivered, and damaged assets are a common occurrence in shipment or asset tracking. Disclosed are various embodiments concerning a battery-less or intermittent battery use environments in which a node uses internal logic (e.g., circuitry and/or software) that, based at least in part on sensor information and stored information regarding the history of the node, may track events that have occurred to the node. The node may be responsive to events and determine whether exceptions have occurred that require attention. For example, detecting damage might cause the node to update an output to indicate the node and associated material, if any, needs to be rerouted to address the exception.
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公开(公告)号:US11609784B2
公开(公告)日:2023-03-21
申请号:US15955731
申请日:2018-04-18
Applicant: Intel Corporation
Inventor: Thijs Metsch , Leonard Feehan , Annie Ibrahim Rana , Rahul Khanna , Sharon Ruane , Marcin Spoczynski
Abstract: A method for distributing at least one computational process amongst shared resources is proposed. At least two shared resources capable of performing the computational process are determined. According to the method, a workload characteristic for each of the shared resources is predicted. The workload characteristic accounts for at least two subsystems of each shared resource. One of the at least two shared resources is selected based on the predicted workload characteristics.
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公开(公告)号:US20210318823A1
公开(公告)日:2021-10-14
申请号:US17214605
申请日:2021-03-26
Applicant: Intel Corporation
Inventor: Susanne M. Balle , Francesc Guim Bernat , Slawomir Putyrski , Joe Grecco , Henry MITCHEL , Rahul Khanna , Evan CUSTODIO
IPC: G06F3/06 , G06F16/174 , G06F21/57 , G06F21/73 , G06F8/65 , H04L12/24 , H04L29/08 , G06F11/30 , G06F9/50 , H01R13/453 , G06F9/48 , H03M7/30 , H03M7/40 , H04L12/26 , H04L12/813 , H04L12/851 , G06F11/07 , G06F11/34 , G06F7/06 , G06T9/00 , H03M7/42 , H04L12/28 , H04L12/46 , H04L29/12 , G06F13/16 , G06F21/62 , G06F21/76 , H03K19/173 , H04L9/08 , H04L12/933 , G06F9/38 , G06F12/02 , G06F12/06 , G06T1/20 , G06T1/60 , G06F9/54 , G06F8/656 , G06F8/658 , G06F8/654 , G06F9/4401 , H01R13/631 , H05K7/14
Abstract: Technologies for offloading acceleration task scheduling operations to accelerator sleds include a compute device to receive a request from a compute sled to accelerate the execution of a job, which includes a set of tasks. The compute device is also to analyze the request to generate metadata indicative of the tasks within the job, a type of acceleration associated with each task, and a data dependency between the tasks. Additionally the compute device is to send an availability request, including the metadata, to one or more micro-orchestrators of one or more accelerator sleds communicatively coupled to the compute device. The compute device is further to receive availability data from the one or more micro-orchestrators, indicative of which of the tasks the micro-orchestrator has accepted for acceleration on the associated accelerator sled. Additionally, the compute device is to assign the tasks to the one or more micro-orchestrators as a function of the availability data.
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公开(公告)号:US11095755B2
公开(公告)日:2021-08-17
申请号:US15645516
申请日:2017-07-10
Applicant: INTEL CORPORATION
Inventor: Francesc Guim Bernat , Susanne M. Balle , Rahul Khanna , Karthik Kumar
Abstract: A host fabric interface (HFI), including: first logic to communicatively couple a host to a fabric; and second logic to provide a disaggregated telemetry engine (DTE) to: receive notification via the fabric of available telemetry data for a remote accelerator; allocate memory for handling the telemetry data; and receive the telemetry data from the disaggregated accelerator.
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公开(公告)号:US10986005B2
公开(公告)日:2021-04-20
申请号:US15638855
申请日:2017-06-30
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Susanne M. Balle , Rahul Khanna , Sujoy Sen , Karthik Kumar
IPC: H04L12/26 , G06F16/901 , H04B10/25 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/30 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04L12/24 , H04L12/931 , H04L12/947 , H04L29/08 , H04L29/06 , H04Q11/00 , H05K7/14 , G06F9/38 , G06F9/50 , H04L12/851 , H04L12/811 , H05K5/02 , H04W4/80 , G06Q10/08 , G06Q10/00 , G06Q50/04 , H04L12/911 , B25J15/00 , B65G1/04 , H05K7/20 , H04L12/939 , H04W4/02 , H04L12/751 , G06F13/42 , H05K1/18 , G05D23/19 , G05D23/20 , H04L12/927 , H05K1/02 , H04L12/781 , H04Q1/04 , G06F12/0893 , H05K13/04 , G11C5/06 , G06F11/14 , G06F11/34 , G06F12/0862 , G06F15/80 , H04L12/919 , G06F12/10 , G06Q10/06 , G07C5/00 , H04L12/28 , H04L29/12 , H04L9/06 , H04L9/14 , H04L9/32 , H04L12/933
Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
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公开(公告)号:US10897505B2
公开(公告)日:2021-01-19
申请号:US15721697
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Christopher R. Carlson , Greeshma Pisharody , Rahul Khanna , Arvind G. Kumar
Abstract: A technology is described for a wireless sensor network. An example method may include detecting an aircraft takeoff preparation event using cabin air pressure data and accelerometer data indicating that an aircraft is preparing for takeoff. Transmitting a listen command to sensor nodes included in a sensor network, the listen command instructing the sensor nodes to disable the wireless network transmissions and listen for commands transmitted by the gateway. Disabling gateway wireless transmissions to the sensor nodes and a computing network. Detecting a landing event using the cabin air pressure data and the accelerometer data indicating that the aircraft has landed. Enabling the gateway wireless transmissions to the sensor nodes and the computing network, and transmitting an enable command to the sensor nodes included in the sensor network, the enable command instructing the sensor nodes to enable the wireless network transmissions and resume sending sensor data to the gateway.
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