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    CONTROL OF POWER STATE IN COMPUTER PROCESSOR
    32.
    发明公开
    CONTROL OF POWER STATE IN COMPUTER PROCESSOR 审中-公开

    公开(公告)号：US20240004454A1

    公开(公告)日：2024-01-04

    申请号：US17809652

    申请日：2022-06-29

    Applicant: Intel Corporation

    Inventor： Sagar C. Pawar ,  Pannerkumar Rajagopal ,  Raghavendra Nagaraj ,  Ovais F. Pir ,  Prakash Pillai

    IPC: G06F1/3296 ,  G06F1/30

    CPC classification number: G06F1/3296 ,  G06F1/30

    Abstract: In an embodiment, a processor may include processing circuits to execute instructions. The processor may also include at least one circuit to: detect a management mode trigger event during operation of the processor in a first power state, the management mode trigger event to initiate a management mode in the processor; in response to a detection of the management mode trigger event, switch the processor from the first power state to a second power state; and after a switch of the processor from the first power state to the second power state, initiate the management mode in the processor. Other embodiments are described and claimed.

    POWER MANAGEMENT OF A PROCESSOR AND A PLATFORM IN ACTIVE STATE AND LOW POWER STATE
    34.
    发明申请
    POWER MANAGEMENT OF A PROCESSOR AND A PLATFORM IN ACTIVE STATE AND LOW POWER STATE 有权

    公开(公告)号：US20220391003A1

    公开(公告)日：2022-12-08

    申请号：US17702504

    申请日：2022-03-23

    Applicant: Intel Corporation

    Inventor： Pannerkumar Rajagopal ,  Raghavendra N ,  Ovais Pir ,  Prakash Pillai ,  Sagar C. Pawar

    IPC: G06F1/3231

    Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

    DYNAMIC ADJUSTMENT OF AUDIO PRODUCTION
    38.
    发明申请
    DYNAMIC ADJUSTMENT OF AUDIO PRODUCTION 有权
    动态调整音像制作

    公开(公告)号：US20160364207A1

    公开(公告)日：2016-12-15

    申请号：US14739954

    申请日：2015-06-15

    Applicant: Intel Corporation

    Inventor： Sagar C. Pawar ,  Prakash Pillai

    IPC: G06F3/16

    CPC classification number: G06F3/165

    Abstract: Apparatuses, methods, and computer-readable media for dynamic configuration of audio production are described. Audio production nodes (“APNs”) may produce audio. The APNs and may be configured to be compliant with a Precision Time Protocol (“PTP”). The APNs may be configured to perform dynamic configuration of audio production. An APN may receive configuration-related information transmitted from one or more other APNs, such as in association with operation of the PTP. An APN, in response to receipt of this configuration-related data, may modify configuration settings used for its audio production such as modification of timing, tone, power, intensity, equalization settings, or other configuration settings. The APN may be configured to produce its own configuration-related data for use by other APNs to modify the other APNs' configuration settings. Other embodiments may be described and/or claimed.

    Abstract translation: 描述了用于音频制作的动态配置的装置，方法和计算机可读介质。 音频制作节点（“APN”）可能产生音频。 APN并且可以被配置为符合精确时间协议（“PTP”）。 APN可以被配置为执行音频制作的动态配置。 APN可以接收从一个或多个其他APN发送的配置相关信息，例如与PTP的操作相关联。 响应于接收到该配置相关数据，APN可以修改用于其音频制作的配置设置，例如修改定时，音调，功率，强度，均衡设置或其他配置设置。 APN可以被配置为产生其自己的配置相关数据，供其他APN使用以修改其他APN的配置设置。 可以描述和/或要求保护其他实施例。

    WIRELESSLY PROVIDING POWER TO A FULLY DISCHARGED BATTERY
    39.
    发明申请
    WIRELESSLY PROVIDING POWER TO A FULLY DISCHARGED BATTERY 审中-公开
    无偿地将电力提供给完全放电的电池

    公开(公告)号：US20160352134A1

    公开(公告)日：2016-12-01

    申请号：US14725586

    申请日：2015-05-29

    Applicant: INTEL CORPORATION

    Inventor： Sagar C. Pawar ,  Prakash Pillai

    IPC: H02J7/02 ,  H02J7/04

    CPC classification number: H02J7/025 ,  H02J7/042 ,  H02J50/10 ,  H02J50/80

    Abstract: Techniques for wireless charging in a system, method, and apparatus are described herein. An apparatus for charging at a wireless power receiver may include logic. The logic is configured to supply voltage received at the wireless power receiver at a first power level to a battery that is initially fully discharged, wherein the power of the first power level is received during a predefined interval of a fully discharged battery protocol. The logic is to monitor a second power level available at the battery, and initiate a wireless handshake with a wireless power transmitter inductively coupled to the wireless power receiver indicating configurations of the wireless power receiver upon detection of the second power level meeting or exceeding a predefined threshold.

    Abstract translation: 本文中描述了用于系统，方法和装置中的无线充电的技术。 用于在无线电力接收器处充电的装置可以包括逻辑。 该逻辑被配置为将第一功率电平处的在无线电力接收器接收的电压提供给初始完全放电的电池，其中在完全放电的电池协议的预定间隔期间接收第一功率电平的功率。 逻辑是监视电池可用的第二功率电平，并且发射无线电力发射器的无线握手，所述无线电力发射机感应地耦合到无线电力接收器，指示无线电力接收机的配置在检测到第二功率电平会议或超过预定义 阈。

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