公开(公告)号：US10653026B2

公开(公告)日：2020-05-12

申请号：US15864583

申请日：2018-01-08

Applicant: Intel Corporation

Inventor： Samarth Alva ,  Krishnakumar Varadarajan ,  Yogesh Channaiah ,  Prakash Pillai ,  Sagar Pawar ,  Aneesh Tuljapurkar ,  Raghavendra N

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  H05K5/02 ,  G06K7/10 ,  H01F7/02

Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.

公开(公告)号：US20180293291A1

公开(公告)日：2018-10-11

申请号：US15481733

申请日：2017-04-07

Applicant: INTEL CORPORATION

Inventor： Sagar C. Pawar ,  Prakash Pillai ,  Raghavendra N ,  Aneesh A. Tuljapurkar

IPC: G06F17/30 ,  H04L27/26 ,  H04L7/00 ,  H04L29/08 ,  H04L7/10

CPC classification number: G06F17/30575 ,  G06F1/04 ,  H04J3/06 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/10

Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting. Other embodiments are described and claimed.

公开(公告)号：US20210373833A1

公开(公告)日：2021-12-02

申请号：US16890798

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Sagar Pawar ,  Prakash Pillai ,  Ovais Pir ,  Murali Iyengar ,  Pannerkumar Rajagopal ,  Raghavendra N ,  Aneesh Tuljapurkar

IPC: G06F3/14 ,  G06F3/0487 ,  G09G3/34

Abstract: Techniques and mechanisms for power management of display devices based on an indication that a user exhibits interest in one, but not all, of said display devices. In an embodiment, logic of a computer device identifies a condition wherein a user of the computer device exhibits insufficient interest in a first display device, while exhibiting at least some interest user in a second display device. The first display device and the second display device support an extended display mode of an operating system. Based on the condition, the logic automatically reduces a consumption of power by the first display device. Of the first display device and the second display device, only the first display device is subjected to a power state transition based on the condition.

公开(公告)号：US10747779B2

公开(公告)日：2020-08-18

申请号：US16426029

申请日：2019-05-30

Applicant: Intel Corporation

Inventor： Sagar C. Pawar ,  Prakash Pillai ,  Raghavendra N ,  Aneesh A. Tuljapurkar

IPC: G06F15/16 ,  G06F16/27 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3296 ,  G06F1/324 ,  H04J3/06

Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting. Other embodiments are described and claimed.

公开(公告)号：US10318547B2

公开(公告)日：2019-06-11

申请号：US15481733

申请日：2017-04-07

Applicant: INTEL CORPORATION

Inventor： Sagar C. Pawar ,  Prakash Pillai ,  Raghavendra N ,  Aneesh A. Tuljapurkar

IPC: G06F15/16 ,  G06F16/27 ,  H04L7/00 ,  H04L7/10 ,  G06F1/04 ,  H04J3/06

Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting. Other embodiments are described and claimed.

公开(公告)号：US11432421B2

公开(公告)日：2022-08-30

申请号：US16847106

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Samarth Alva ,  Krishnakumar Varadarajan ,  Yogesh Channaiah ,  Prakash Pillai ,  Sagar Pawar ,  Aneesh Tuljapurkar ,  Raghavendra N

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  H05K5/02 ,  G06K7/10 ,  H01F7/02

Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.

公开(公告)号：US20220198022A1

公开(公告)日：2022-06-23

申请号：US17132844

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Sagar C. Pawar ,  Pannerkumar Rajagopal ,  Raghavendra N ,  Prakash Pillai ,  Ovais Pir

IPC: G06F21/57 ,  G06F1/18 ,  G06F21/32 ,  G06F1/3215 ,  G06F1/26

Abstract: A power-up scheme for a computing system that applies a biometric sensor (e.g., a fingerprint sensor, eye sensor, etc.) to authenticate a user before enabling power-up of the computing system or to resume transition to a power state (e.g., one of the power states defined by the Advance Configuration and Power Interface (ACPI)). Output of the biometric sensor is compared against data of a registered user for a match. The data may include an original copy of an output of the biometric sensor saved in a non-volatile memory (e.g., serial peripheral interface (SPI) flash device). If a match exists, a logic in the computing system will allow the computing system to power-up. In the absence of a match, the computing system will not be powered up. In some examples, battery charging is also disabled if the match is not found.

公开(公告)号：US20200125579A1

公开(公告)日：2020-04-23

申请号：US16426029

申请日：2019-05-30

Applicant: Intel Corporation

Inventor： Sagar C. Pawar ,  Prakash Pillai ,  Raghavendra N ,  Aneesh A. Tuljapurkar

IPC: G06F16/27 ,  G06F1/04 ,  H04J3/06 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/12

Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overlocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting. Other embodiments are described and claimed.

公开(公告)号：US12007823B2

公开(公告)日：2024-06-11

申请号：US17702504

申请日：2022-03-23

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Raghavendra N ,  Ovais Pir ,  Prakash Pillai ,  Sagar C. Pawar

IPC: G06F1/32 ,  G06F1/3231

CPC classification number: G06F1/3231

Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

公开(公告)号：US11895803B2

公开(公告)日：2024-02-06

申请号：US16914311

申请日：2020-06-27

Applicant: INTEL CORPORATION

Inventor： Krishnakumar Varadarajan ,  Arvind Sundaram ,  Srinivasarao Konakalla ,  Yogesh Channaiah ,  Satyajit Siddharay Kamat ,  Raghavendra N

IPC: H05K7/20 ,  F04D25/06 ,  F04D29/58 ,  F04D17/16 ,  G06F1/20 ,  F04D29/28

CPC classification number: H05K7/20172 ,  F04D17/16 ,  F04D25/0606 ,  F04D29/281 ,  F04D29/5806 ,  F04D29/5813 ,  G06F1/203

Abstract: Particular embodiments described herein provide for an electronic device that includes a fan. The fan can include a center shaft, fan blades that extend from the center shaft, and a plurality of magnets on an outside portion of at least two of the fan blades, where stator coils interact with the magnets to drive the blades around the center shaft. The center shaft and fan blades are a single component from the same material. In some examples, the center shaft and fan blades were created using a metal injection molding process.