公开(公告)号：US20060107175A1

公开(公告)日：2006-05-18

申请号：US10977914

申请日：2004-10-29

申请人： Timothy Dell ,  Kevin Gower ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Warren Maule

IPC分类号： H03M13/00

CPC分类号： G11C5/04

摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

公开(公告)号：US20060095701A1

公开(公告)日：2006-05-04

申请号：US10977038

申请日：2004-10-29

申请人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F13/00

CPC分类号： G06F13/1673 ,  G06F13/1689

摘要： A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.

公开(公告)号：US20060095629A1

公开(公告)日：2006-05-04

申请号：US10977921

申请日：2004-10-29

申请人： Kevin Gower ,  Warren Maule ,  Juergen Saalmueller

发明人： Kevin Gower ,  Warren Maule ,  Juergen Saalmueller

IPC分类号： G06F13/14

CPC分类号： G06F13/4243

摘要： A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.

摘要翻译： 用于向存储器系统提供服务接口的级联互连系统。 级联互联系统包括主服务接口模块，业务接口总线以及一个或多个从业务接口模块。 主服务接口模块和从接口模块通过业务接口总线级联互联。 每个从业务接口模块与相应的存储器模块通信，用于向存储器模块提供服务。

公开(公告)号：US20060036827A1

公开(公告)日：2006-02-16

申请号：US10903188

申请日：2004-07-30

申请人： Timothy Dell ,  Frank Ferraiolo ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Timothy Dell ,  Frank Ferraiolo ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： G06F11/201 ,  G06F11/104

摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.