公开(公告)号：US20060036827A1

公开(公告)日：2006-02-16

申请号：US10903188

申请日：2004-07-30

申请人： Timothy Dell ,  Frank Ferraiolo ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Timothy Dell ,  Frank Ferraiolo ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： G06F11/201 ,  G06F11/104

摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.

公开(公告)号：US20060036826A1

公开(公告)日：2006-02-16

申请号：US10903182

申请日：2004-07-30

申请人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G06F13/1684

摘要： A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data rate. The memory controller and the memory modules are interconnected by a packetized multi-transfer interface via the memory busses.

摘要翻译： 用于提供总线速度倍增器的存储器子系统。 存储器子系统包括以存储器模块数据速率操作的一个或多个存储器模块。 存储器子系统还包括存储器控制器和一个或多个存储器总线。 存储器总线的操作是内存模块数据速率的四倍。 存储器控制器和存储器模块通过分组化的多传输接口经由存储器总线互连。

公开(公告)号：US20070255902A1

公开(公告)日：2007-11-01

申请号：US11773660

申请日：2007-07-05

申请人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F13/4022

摘要： A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

摘要翻译： 包括多个存储器组件的分组级联存储器系统，包括多个段的存储器总线，总线中继器模块和段级备用模块。 总线中继器模块经由存储器总线与两个或多个存储器组件通信。 段级保护模块在段故障时为通信总线提供段级备用。

公开(公告)号：US20060026349A1

公开(公告)日：2006-02-02

申请号：US10903178

申请日：2004-07-30

申请人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F13/4022

摘要： A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

摘要翻译： 包括多个存储器组件的分组级联存储器系统，包括多个段的存储器总线，总线中继器模块和段级备用模块。 总线中继器模块经由存储器总线与两个或多个存储器组件通信。 段级保护模块在段故障时为通信总线提供段级备用。

公开(公告)号：US20060095701A1

公开(公告)日：2006-05-04

申请号：US10977038

申请日：2004-10-29

申请人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

发明人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

IPC分类号： G06F13/00

CPC分类号： G06F13/1673 ,  G06F13/1689

摘要： A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.

公开(公告)号：US20050240801A1

公开(公告)日：2005-10-27

申请号：US10818569

申请日：2004-04-06

申请人： Judy Johnson ,  Kevin Kark ,  George Wellwood

发明人： Judy Johnson ,  Kevin Kark ,  George Wellwood

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F11/106

摘要： Memory is scrubbed by an improved non-linear method giving scrubbing preference to the central storage region having the characteristic of a high risk read-only memory such as the CPA region to prevent the accumulation of temporary data errors. The chip row on which the CPA resides is scrubbed after each time the scrubbing of a non-CPA chip row in a PMA completed successfully. The next non-CPA least recently scrubbed chip row would be selected for scrubbing after scrubbing completed on the CPA chip row. This in a first case provides non-linear selection methods of scrubbing central storage of computer systems to more frequently select (“select” herein encompasses the meaning of “favor”) scrub regions having the characteristic of a predominately read-only memory making those regions at a higher risk of failure than those regions having lower risk because of frequent write operations. In a second case, scrub regions having the characteristic of a predominately read-only memory are selected by using a second preferred embodiment selection method which uses the detection of faulty data from normal system accesses to central storage to identify other high risk regions and scrub them before other lower risk regions. In addition, the severity of the detected data error can be used to determine the rate at which scrub commands are sent to the selected region: the higher the severity, the higher the scrub rate.

摘要翻译： 通过改进的非线性方法对存储器进行擦除，从而对具有诸如CPA区域的高风险只读存储器的特征的中央存储区域进行擦除偏好以防止临时数据错误的累积。 在每次擦除PMA中的非CPA芯片行之后，CPA所在的芯片行被擦除，成功完成。 在CPA芯片行上完成擦洗之后，将选择下一个非CPA最近擦洗的芯片行进行擦洗。 这在第一种情况下提供了用于擦洗计算机系统的中央存储的非线性选择方法以更频繁地选择（“选择”在本文中包括“有利”的含义）具有主要只读存储器的特征的擦洗区域，使得这些区域 由于频繁的写入操作，风险较高的地区的风险较高。 在第二种情况下，通过使用第二优选实施例的选择方法来选择具有主要是只读存储器的特征的擦除区域，该方法使用检测来自中央存储器的正常系统访问的故障数据来识别其他高风险区域并擦除它们 在其他较低风险地区之前。 此外，检测到的数据错误的严重性可用于确定擦除命令发送到所选区域的速率：严重性越高，擦除率越高。

公开(公告)号：US20060212726A1

公开(公告)日：2006-09-21

申请号：US11082123

申请日：2005-03-16

申请人： Liyong Wang ,  Kevin Kark

发明人： Liyong Wang ,  Kevin Kark

IPC分类号： G06F1/26

CPC分类号： G06F1/32

摘要： A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the governors keep counting its local power consumption. Each time the number passes a governor, the governor will add its local count onto this number, store this number for future usage, and reset its local count. When the new number returns back to the same power governor, the governor will subtract the new number with its stored number to calculate the overall system power usage within a number circulation period. The system power number overflow problem is also detected with a counter if the incoming number is smaller then the number previously stored. The counter whose counting capacity is greater than the maximum system power usage on all the nodes within a number circulation period. A single number transfer mode and multiple number transfer mode and heterogeneous multi-node components which could have different power usage configurations are employed.

摘要翻译： 调节多节点计算机系统组件功率的方法具有连接所有功率调节器的闭环路径，并且在环路中循环是表示整个系统的功耗的系统功率数。 同时，所有的省长都不断地计算当地的电力消耗。 每当该号码通过州长时，州长会将其本地计数添加到该号码上，存储此号码以供将来使用，并重置其本地计数。 当新号码返回相同的调速器时，总监将以其存储号码减去新号码，以计算数字循环期间的整体系统功率使用情况。 如果输入的数字小于先前存储的数字，则也会使用计数器检测系统电源数量溢出问题。 计数器的计数能力大于数字循环周期内所有节点的最大系统功耗。 采用可以具有不同功率使用配置的单个传输模式和多个传输模式和异构多节点组件。

公开(公告)号：US20080065915A1

公开(公告)日：2008-03-13

申请号：US11937980

申请日：2007-11-09

申请人： Liyong Wang ,  Kevin Kark

发明人： Liyong Wang ,  Kevin Kark

IPC分类号： G06F1/26

CPC分类号： G06F1/32

摘要： A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the governors keep counting its local power consumption. Each time the number passes a governor, the governor will add its local count onto this number, store this number for future usage, and reset its local count. When the new number returns back to the same power governor, the governor will subtract the new number with its stored number to calculate the overall system power usage within a number circulation period. The system power number overflow problem is also detected with a counter if the incoming number is smaller then the number previously stored. The counter whose counting capacity is greater than the maximum system power usage on all the nodes within a number circulation period. A single number transfer mode and multiple number transfer mode and heterogeneous multi-node components which could have different power usage configurations are employed.

摘要翻译： 调节多节点计算机系统组件功率的方法具有连接所有功率调节器的闭环路径，并且在环路中循环是表示整个系统的功耗的系统功率数。 同时，所有的省长都不断地计算当地的电力消耗。 每当该号码通过州长时，州长会将其本地计数添加到该号码上，存储此号码以供将来使用，并重置其本地计数。 当新号码返回相同的调速器时，总监将以其存储号码减去新号码，以计算数字循环期间的整体系统功率使用情况。 如果输入的数字小于先前存储的数字，则也会使用计数器检测系统电源数量溢出问题。 计数器的计数能力大于数字循环周期内所有节点的最大系统功耗。 采用可以具有不同功率使用配置的单个传输模式和多个传输模式和异构多节点组件。

公开(公告)号：US20080065914A1

公开(公告)日：2008-03-13

申请号：US11934799

申请日：2007-11-05

申请人： Kevin Kark ,  Liyong Wang

发明人： Kevin Kark ,  Liyong Wang

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G11C5/14 ,  G11C11/4074

摘要： A method for regulating system power using a power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.

摘要翻译： 在调节整个计算机系统的存储器功耗的多节点计算机系统中使用用于DRAM的功率调节器来调节系统功率的方法采用闭环，其连接系统内的所有功率调节器，使得它们能够一致地工作，使得 每个功率调节器都具有整个系统内的记忆活动知识。 然后，它们基于真正的总体测量来控制和限制内存使用，而不仅仅是本地测量。 每个节点功率调节器具有存储器命令计数器，振铃号接收器，振铃号发射器，调速器激活控制器和存储器流量控制器。 每个节点功率调节器计算存储器命令的权重。 当调速器处于活动状态时，可以对实际记忆活动的限制程度进行编程。 此外，命令优先级也可以在激活中进行调整。 可以采用具有节点功率结构的混合环结构以经济地实现最快的数量循环速度。

公开(公告)号：US20060212725A1

公开(公告)日：2006-09-21

申请号：US11081115

申请日：2005-03-16

申请人： Kevin Kark ,  Liyong Wang

发明人： Kevin Kark ,  Liyong Wang

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G11C5/14 ,  G11C11/4074

摘要： A power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.

摘要翻译： 在调节整个计算机系统的存储器功耗的多节点计算机系统中的用于DRAM的功率调节器采用闭环，其连接系统内的所有功率调节器，使得它们能够协调工作，使得每个功率调节器具有 知识在整个系统内的记忆活动。 然后，它们基于真正的总体测量来控制和限制内存使用，而不仅仅是本地测量。 每个节点功率调节器具有存储器命令计数器，振铃号接收器，振铃号发射器，调速器激活控制器和存储器流量控制器。 每个节点功率调节器计算存储器命令的权重。 当调速器处于活动状态时，可以编程限制实际记忆活动的程度。 此外，命令优先级也可以在激活中进行调整。 可以采用具有节点功率结构的混合环结构以经济地实现最快的数量循环速度。