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21 条记录 (耗时 0.028 秒)

    System, method and storage medium for providing a bus speed multiplier
    1.
    发明申请
    System, method and storage medium for providing a bus speed multiplier 审中-公开
    用于提供总线速度倍增器的系统，方法和存储介质

    公开(公告)号：US20060036826A1

    公开(公告)日：2006-02-16

    申请号：US10903182

    申请日：2004-07-30

    申请人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

    发明人： Timothy Dell ,  Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4243 ,  G06F13/1684

    摘要： A memory subsystem for providing a bus speed multiplier. The memory subsystem includes one or more memory modules operating at a memory module data rate. The memory subsystem also includes a memory controller and one or more memory busses. The memory busses operate at four times the memory module data rate. The memory controller and the memory modules are interconnected by a packetized multi-transfer interface via the memory busses.

    摘要翻译： 用于提供总线速度倍增器的存储器子系统。 存储器子系统包括以存储器模块数据速率操作的一个或多个存储器模块。 存储器子系统还包括存储器控制器和一个或多个存储器总线。 存储器总线的操作是内存模块数据速率的四倍。 存储器控制器和存储器模块通过分组化的多传输接口经由存储器总线互连。

    SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING A SERIALIZED MEMORY INTERFACE WITH A BUS REPEATER
    2.
    发明申请
    SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING A SERIALIZED MEMORY INTERFACE WITH A BUS REPEATER 失效
    用BUS提供串行存储器接口的系统，方法和存储介质

    公开(公告)号：US20070255902A1

    公开(公告)日：2007-11-01

    申请号：US11773660

    申请日：2007-07-05

    申请人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

    发明人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

    IPC分类号： G06F12/00 ,  G06F12/10

    CPC分类号： G06F13/4022

    摘要： A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

    摘要翻译： 包括多个存储器组件的分组级联存储器系统，包括多个段的存储器总线，总线中继器模块和段级备用模块。 总线中继器模块经由存储器总线与两个或多个存储器组件通信。 段级保护模块在段故障时为通信总线提供段级备用。

    System, method and storage medium for providing a serialized memory interface with a bus repeater
    3.
    发明申请
    System, method and storage medium for providing a serialized memory interface with a bus repeater 失效
    用于向总线中继器提供串行存储器接口的系统，方法和存储介质

    公开(公告)号：US20060026349A1

    公开(公告)日：2006-02-02

    申请号：US10903178

    申请日：2004-07-30

    申请人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

    发明人： Kevin Gower ,  Kevin Kark ,  Mark Kellogg ,  Warren Maule

    IPC分类号： G06F12/00 ,  G06F12/10

    CPC分类号： G06F13/4022

    摘要： A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

    摘要翻译： 包括多个存储器组件的分组级联存储器系统，包括多个段的存储器总线，总线中继器模块和段级备用模块。 总线中继器模块经由存储器总线与两个或多个存储器组件通信。 段级保护模块在段故障时为通信总线提供段级备用。

    SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING DATA CACHING AND DATA COMPRESSION IN A MEMORY SUBSYSTEM
    7.
    发明申请
    SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING DATA CACHING AND DATA COMPRESSION IN A MEMORY SUBSYSTEM 失效
    用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质

    公开(公告)号：US20080016280A1

    公开(公告)日：2008-01-17

    申请号：US11772922

    申请日：2007-07-03

    申请人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

    发明人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

    IPC分类号： G06F12/08

    CPC分类号： G06F13/1684 ,  G06F12/0802 ,  G06F2212/401

    摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

    摘要翻译： 包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。 一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。 存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。 第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

    High reliability memory module with a fault tolerant address and command bus
    9.
    发明申请
    High reliability memory module with a fault tolerant address and command bus 有权

    公开(公告)号：US20060190780A1

    公开(公告)日：2006-08-24

    申请号：US11406717

    申请日：2006-04-20

    申请人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    发明人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    IPC分类号： G11C29/00

    CPC分类号： H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

    HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS
    10.
    发明申请
    HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS 有权

    公开(公告)号：US20070204201A1

    公开(公告)日：2007-08-30

    申请号：US11741319

    申请日：2007-04-27

    申请人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    发明人： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    IPC分类号： G11C29/00

    CPC分类号： H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.