摘要:
A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.
摘要:
In one embodiment, the present invention includes a method for performing a test on a rechargeable battery to indirectly determine a state of protection circuitry associated with the battery. The method may discharge the battery by controlling a pull-down current into a system, determine if the battery voltage falls below a first threshold level within a predetermined amount of time, and if so provide a pre-charge current to the battery.
摘要:
A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.
摘要:
A system and method is provided to improve the jitter performance of high frequency synthesizers used in read/write channel circuits. The frequency synthesizer is implemented with multiple phase locked loops arranged in a cascaded fashion to increase the update rates at which the cascaded loops operate at for a given frequency resolution of the synthesizer. The cascaded or staged phase locked loops may be utilized for generating read, write, and servo clocks for a read/write channel circuit. The cascaded phase locked loops may also be arranged such that one or more stages are shared to generate the read, write or servo clocks.
摘要:
A system and method is disclosed in which a circuit is provided to improve the settling performance of synthesizers used in read/write channel applications when the synthesizer is required to switch frequencies by a small percentage quickly. This is useful in read channel applications where the clock recovery is performed using an all-digital PLL. A digital timing recovery scheme is utilized in which one data frequency synthesizer provides both write and read frequencies. The read frequency is set higher than the write frequency to allow for oversampling when reading data from the storage medium. When changing from a write to read frequency or vice-versa the frequency synthesizer rapidly settles to the new frequency. The frequency synthesizer includes a phase locked loop which utilizes a controllable oscillator. The phase locked loop divisors are changed to obtain the desired frequency changes. An input signal to the controllable oscillator is also changed in order to obtain the rapid settling times. In one embodiment the oscillator is a current controlled oscillator and the control current to the oscillator is modified based on whether the data frequency synthesizer is utilized for a read operation or a write operation.
摘要:
In one embodiment, the present invention includes a method for performing a test on a rechargeable battery to indirectly determine a state of protection circuitry associated with the battery. The method may discharge the battery by controlling a pull-down current into a system, determine if the battery voltage falls below a first threshold level within a predetermined amount of time, and if so provide a pre-charge current to the battery.
摘要:
A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a first timing circuit that provides timed signals to control timing of system operations during an active mode of operation of the digital processing circuit, and a second timing circuit that provides timing signals to control timing of system operations during an active mode of operation of the radio frequency circuit. In one particular embodiment, at least a portion of the first timing circuit is disabled when the radio frequency circuit is active (receiving and/or transmitting).
摘要:
A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.
摘要:
A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.
摘要:
The invention can utilize a switching power regulator and a non-switching power regulator in conjunction to provide regulated power to the digital logic. The digital logic and switching regulator may be deactivated during RF activity so that interference from both the digital circuitry and the switching regulator is significantly reduced. The state of the digital circuitry may be maintained during this standby period by using the non-switching power regulator to provide an as-required leakage current to the digital circuitry in order to maintain state. After the RF event (e.g. sending or receiving data) has concluded, the switching regulator may be activated and digital processing continued using the digital logic with no loss of continuity.