公开(公告)号：US07523265B2

公开(公告)日：2009-04-21

申请号：US11083615

申请日：2005-03-18

申请人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

发明人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0833

摘要： Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

摘要翻译： 考虑了在缓存中促进从共享到独占的系统和布置。 实施例包括高速缓存控制器，其适于确定处理器将要发出仅地址杀死请求的存储器线是否驻留在共享状态下的高速缓存行的填充缓冲器中。 如果是这样，高速缓存控制器可以将填充缓冲区标记为没有完成总线事务并且发出针对该填充缓冲区的仅地址杀死请求。 只有地址的中断请求可以发送到总线上的其他处理器，而其他处理器可以通过使存储器线的高速缓存条目无效来进行响应。 在其他处理器确认之后，总线仲裁器可以确认杀死请求，将已经在该填充缓冲器中的存储器线路推送到独占状态。 一旦被提升，填充缓冲器可以被标记为完成总线事务并且可以被写入高速缓存。

公开(公告)号：US20080313410A1

公开(公告)日：2008-12-18

申请号：US12196705

申请日：2008-08-22

申请人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

发明人： James Norris Dieffenderfer ,  Praveen G. Karandikar ,  Michael Bryan Mitchell ,  Thomas Philip Speier ,  Paul Michael Steinmetz

IPC分类号： G06F12/08

CPC分类号： G06F12/0833

摘要： Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

摘要翻译： 实施例包括高速缓存控制器，其适于确定处理器将要发出仅地址杀死请求的存储器线是否驻留在共享状态下的高速缓存行的填充缓冲器中。 如果是这样，高速缓存控制器可以将填充缓冲区标记为没有完成总线事务并且发出针对该填充缓冲区的仅地址杀死请求。 只有地址的中断请求可以发送到总线上的其他处理器，而其他处理器可以通过使存储器线的高速缓存条目无效来进行响应。 在其他处理器确认之后，总线仲裁器可以确认杀死请求，将已经在该填充缓冲器中的存储器线路推送到独占状态。 一旦被提升，填充缓冲器可以被标记为完成总线事务并且可以被写入高速缓存。

公开(公告)号：US06816962B2

公开(公告)日：2004-11-09

申请号：US10082085

申请日：2002-02-25

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

IPC分类号： G06F930

CPC分类号： G06F9/382 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30181

摘要： A method and system for utilizing bits in a collection of illegal op codes in order to enable pre-decoded instructions to be stored in an instruction cache without increasing the number of bits required to represent the pre-decoded instructions. Upon fetching an instruction from memory, the op code is examined for membership in a collection of illegal op codes. If the instruction op code is a member of this collection, the instruction may be re-encoded to use a different, common illegal op code. If the instruction op code is not a member of the collection of illegal op codes, but is instead an instruction to be stored in the instruction cache in a pre-decoded format, the additional pre-decoded information may be stored in the instruction encoding by utilizing the portion of the op code space which has been vacated by the re-encoding of the illegal op codes.

摘要翻译： 一种用于利用非法操作码集合中的比特的方法和系统，以便能够将预解码的指令存储在指令高速缓存中，而不增加表示预解码指令所需的比特数。 在从存储器获取指令时，检查操作码是否存在非法操作码集合中的成员资格。 如果指令操作代码是该集合的成员，则该指令可能被重新编码以使用不同的，常见的非法操作码。 如果指令操作码不是非法操作码集合的成员，而是以预解码格式代替存储在指令高速缓存中的指令，附加的预解码信息可以被存储在指令编码中 利用由非法操作代码的重新编码已经腾出的操作代码空间的部分。

公开(公告)号：US06948053B2

公开(公告)日：2005-09-20

申请号：US10082144

申请日：2002-02-25

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

IPC分类号： G06F9/00 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/322 ,  G06F9/324 ,  G06F9/3804

摘要： A method and system for calculating a branch target address. Upon fetching a branch instruction from memory, the n−1 lower order bits of the branch target address may be pre-calculated and stored in the branch instruction prior to storing the branch instruction in the instruction cache. Upon retrieving the branch instruction from the instruction cache, the upper order bits of the branch target address may be recovered using the sign bit and the carry bit stored in the branch instruction. The sign bit and the carry bit may be used to select one of three possible upper-order bit value combinations of the branch target address. The selected upper-order bit value combination may then be appended to the n−1 lower order bits of the branch target address to form the complete branch target address.

摘要翻译： 一种用于计算分支目标地址的方法和系统。 在从存储器取出分支指令时，可以在将转移指令存储在指令高速缓存中之前将分支目标地址的n-1个较低位进行预先计算并存储在转移指令中。 在从指令高速缓存中检索分支指令时，可以使用分支指令中存储的符号位和进位位来恢复分支目标地址的高位。 符号位和进位位可用于选择分支目标地址的三个可能的高位位组合之一。 然后可以将所选择的高位比特值组合附加到分支目标地址的n-1个较低位，以形成完整的分支目标地址。