公开(公告)号：US06948053B2

公开(公告)日：2005-09-20

申请号：US10082144

申请日：2002-02-25

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

IPC分类号： G06F9/00 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/322 ,  G06F9/324 ,  G06F9/3804

摘要： A method and system for calculating a branch target address. Upon fetching a branch instruction from memory, the n−1 lower order bits of the branch target address may be pre-calculated and stored in the branch instruction prior to storing the branch instruction in the instruction cache. Upon retrieving the branch instruction from the instruction cache, the upper order bits of the branch target address may be recovered using the sign bit and the carry bit stored in the branch instruction. The sign bit and the carry bit may be used to select one of three possible upper-order bit value combinations of the branch target address. The selected upper-order bit value combination may then be appended to the n−1 lower order bits of the branch target address to form the complete branch target address.

摘要翻译： 一种用于计算分支目标地址的方法和系统。 在从存储器取出分支指令时，可以在将转移指令存储在指令高速缓存中之前将分支目标地址的n-1个较低位进行预先计算并存储在转移指令中。 在从指令高速缓存中检索分支指令时，可以使用分支指令中存储的符号位和进位位来恢复分支目标地址的高位。 符号位和进位位可用于选择分支目标地址的三个可能的高位位组合之一。 然后可以将所选择的高位比特值组合附加到分支目标地址的n-1个较低位，以形成完整的分支目标地址。

公开(公告)号：US06816962B2

公开(公告)日：2004-11-09

申请号：US10082085

申请日：2002-02-25

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Thomas Philip Speier

IPC分类号： G06F930

CPC分类号： G06F9/382 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30181

摘要： A method and system for utilizing bits in a collection of illegal op codes in order to enable pre-decoded instructions to be stored in an instruction cache without increasing the number of bits required to represent the pre-decoded instructions. Upon fetching an instruction from memory, the op code is examined for membership in a collection of illegal op codes. If the instruction op code is a member of this collection, the instruction may be re-encoded to use a different, common illegal op code. If the instruction op code is not a member of the collection of illegal op codes, but is instead an instruction to be stored in the instruction cache in a pre-decoded format, the additional pre-decoded information may be stored in the instruction encoding by utilizing the portion of the op code space which has been vacated by the re-encoding of the illegal op codes.

摘要翻译： 一种用于利用非法操作码集合中的比特的方法和系统，以便能够将预解码的指令存储在指令高速缓存中，而不增加表示预解码指令所需的比特数。 在从存储器获取指令时，检查操作码是否存在非法操作码集合中的成员资格。 如果指令操作代码是该集合的成员，则该指令可能被重新编码以使用不同的，常见的非法操作码。 如果指令操作码不是非法操作码集合的成员，而是以预解码格式代替存储在指令高速缓存中的指令，附加的预解码信息可以被存储在指令编码中 利用由非法操作代码的重新编码已经腾出的操作代码空间的部分。

公开(公告)号：US08661229B2

公开(公告)日：2014-02-25

申请号：US12434804

申请日：2009-05-04

申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3844 ,  G06F9/3804

摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

公开(公告)号：US07650466B2

公开(公告)日：2010-01-19

申请号：US11233575

申请日：2005-09-21

申请人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Robert Douglas Clancy ,  Victor Roberts Augsburg

发明人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Robert Douglas Clancy ,  Victor Roberts Augsburg

IPC分类号： G06F12/00

CPC分类号： G06F12/126

摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.

摘要翻译： 管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。 例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。 响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。 响应于解锁写入，第二个指针是高级的。 第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。 因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

公开(公告)号：US20090210663A1

公开(公告)日：2009-08-20

申请号：US12434804

申请日：2009-05-04

申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/3804

摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

公开(公告)号：US07366877B2

公开(公告)日：2008-04-29

申请号：US10664384

申请日：2003-09-17

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3826 ,  G06F9/3851

摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

摘要翻译： 一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。 在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。 指令问题逻辑根据当指令到达需要的流水线中的阶段时，基于所需操作数将可用的概率来推测来自给定线程的指令。 如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。 一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

公开(公告)号：US20080189521A1

公开(公告)日：2008-08-07

申请号：US12105091

申请日：2008-04-17

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott Mcilvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott Mcilvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3826 ,  G06F9/3851

摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

摘要翻译： 一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。 在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。 指令问题逻辑根据当指令到达要求管道中的阶段时所需操作数将可用的概率推测性地发出给定线程的指令。 如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。 一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

公开(公告)号：US06513134B1

公开(公告)日：2003-01-28

申请号：US09397293

申请日：1999-09-15

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： H02H305

CPC分类号： G06F11/3632 ,  G06F11/3636

摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. Various features, individually and in combination, provide a real-time trace-forward and trace-back capability with a minimal number of pins running at a minimal frequency relative to the processor.

摘要翻译： 一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。 非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。 跟踪技术监视来自代码的正常执行流的指令流程的变化。 各种功能，单独和组合，提供实时跟踪和追溯功能，最少数量的引脚以相对于处理器的最小频率运行。

公开(公告)号：US07587580B2

公开(公告)日：2009-09-08

申请号：US11050932

申请日：2005-02-03

申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3844 ,  G06F9/3804

摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

公开(公告)号：US07454538B2

公开(公告)日：2008-11-18

申请号：US11128135

申请日：2005-05-11

申请人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

发明人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

IPC分类号： G06F3/00

CPC分类号： G06F13/4059 ,  G06F5/06 ,  G06F2205/126

摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

摘要翻译： 来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。 源端计数器跟踪FIFO中可用的空间。 在公开的示例中，初始计数器值对应于FIFO深度。 响应于来自源域的数据就绪信号，计数器无延迟地递减。 响应于来自接收器域的信令从FIFO读取数据，计数器递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器指示FIFO已满时，源可能再发送一次数据。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。