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35 条记录 (耗时 0.025 秒)

    Method of communication in a radio frequency identification system
    32.
    发明授权
    Method of communication in a radio frequency identification system 失效
    射频识别系统中的通信方法

    公开(公告)号：US06763996B2

    公开(公告)日：2004-07-20

    申请号：US09955345

    申请日：2001-09-18

    申请人： Patrick L. Rakers ,  Timothy James Collins ,  Richard Stanley Rachwalski ,  Michael L. Bushman

    发明人： Patrick L. Rakers ,  Timothy James Collins ,  Richard Stanley Rachwalski ,  Michael L. Bushman

    IPC分类号： G06F1700

    CPC分类号： G06K19/0723 ,  G06K7/0008

    摘要： In accordance with the present invention, a radio frequency identification (RFID) device comprises a plurality of data fields. The RFID device transmits a data symbol from a data field, receives an acknowledgement symbol, and compares the transmitted data symbol to the received acknowledgement symbol. The RFID device repeats these steps until data transmission is complete as long as each transmitted data symbol is equivalent to a corresponding received acknowledgement symbol; otherwise, the RFID device maintains the data field from which the last data symbol was transmitted, and temporarily suspends data transmission. When the RFID receives a request for RFID devices temporarily suspended in a given data field to resume data transmission, if the given data field in the request is equivalent to the data field that was maintained, the RFID device repeats the steps above starting with the first symbol in the data field that was maintained.

    摘要翻译： 根据本发明，射频识别（RFID）设备包括多个数据字段。 RFID设备从数据字段发送数据符号，接收确认符号，并将发送的数据符号与接收到的确认符号进行比较。 RFID设备重复这些步骤直到数据传输完成，只要每个发送的数据符号等同于相应的接收的确认符号; 否则，RFID设备维护发送最后一个数据符号的数据字段，并暂时暂停数据传输。 当RFID接收到暂时停留在给定数据字段中的RFID设备的请求以恢复数据传输时，如果请求中的给定数据字段等同于维护的数据字段，则RFID设备重复上述步骤，从第一 在维护的数据字段中的符号。

    Redundant signed digit A-to-D conversion circuit and method thereof
    33.
    发明授权
    Redundant signed digit A-to-D conversion circuit and method thereof 失效
    冗余有符号数字A转D电路及其方法

    公开(公告)号：US5644313A

    公开(公告)日：1997-07-01

    申请号：US463818

    申请日：1995-06-05

    申请人： Patrick L. Rakers ,  Douglas A. Garrity

    发明人： Patrick L. Rakers ,  Douglas A. Garrity

    IPC分类号： H03M1/06 ,  H03M1/40

    CPC分类号： H03M1/403 ,  H03M1/0682

    摘要： RSD n-bit analog-to-digital converter (10) receives voltage VIN that is compared to reference voltages VH and VL in the first stage (18). A digital code, representing VIN, is generated at first stage outputs (24, 26). First stage residue voltage V22 is compared to VH and VL in the second stage (30). A digital code generated at the outputs (28, 32) of the second stage, represent residue voltage V22. Residue voltage V22 is recycled through the first and second stages. Upon reaching the n.sup.th conversion bit, residue voltage V22 of the n.sup.th -1 bit is compared to second stage mid-level voltage reference VMID. A digital code generated at the outputs of the second stage represents the n.sup.th -1 bit residue voltage V22. The digital codes are stored in storage elements (34) and added in a binary adder (38) to provide the n-bit representation of VIN.

    摘要翻译： RSD n位模数转换器（10）接收与第一级（18）中的参考电压VH和VL相比较的电压VIN。 代表VIN的数字代码在第一级输出（24,26）产生。 将第一级残留电压V22与第二级（30）中的VH和VL进行比较。 在第二级的输出端（28,32）产生的数字码表示残留电压V22。 残余电压V22通过第一和第二阶段再循环。 在到达第n个转换位时，将第n-1位的残余电压V22与第二级中间电平参考VMID进行比较。 在第二级的输出处产生的数字代码表示第n位残留电压V22。 数字代码被存储在存储元件（34）中并被加到二进制加法器（38）中以提供VIN的n位表示。

    Current source for reducing noise glitches generated in a digital to analog converter and method therefor
    34.
    发明授权
    Current source for reducing noise glitches generated in a digital to analog converter and method therefor 失效
    用于减少数模转换器中产生的噪声毛刺的电流源及其方法

    公开(公告)号：US5625360A

    公开(公告)日：1997-04-29

    申请号：US524095

    申请日：1995-09-05

    申请人： Douglas A. Garrity ,  Patrick L. Rakers

    发明人： Douglas A. Garrity ,  Patrick L. Rakers

    IPC分类号： H03M1/08 ,  H03M1/66 ,  H03M1/74

    CPC分类号： H03M1/0863 ,  H03M1/662 ,  H03M1/742

    摘要： A switchable current source (41) for a Digital to Analog Converter (DAC) to reduce noise glitches when a change in total current provided by the DAC occurs. The switchable current source (41) is one of many required by a DAC to convert a digital signal to an analog signal. Each current source of the DAC receives an input voltage that enables or disables the current source from providing or not providing a current. A sampled input voltage is alternately provided to the switchable current source (41) by a first flip flop (42) or a second flip flop (43). One flip flop samples the input voltage while the other provides a previous sampled input voltage for enabling and disabling the switchable current source (41). Switches (46,47) couple an output voltage of the first or second flip flops (42,43) a predetermined time after the output voltage changes to a transistor (51) coupled to a current source (53).

    摘要翻译： 用于数模转换器（DAC）的可切换电流源（41），用于在发生DAC提供的总电流变化时减少噪声毛刺。 可切换电流源（41）是DAC将数字信号转换为模拟信号的许多要求之一。 DAC的每个电流源接收输入电压，其使能或禁止当前源提供或不提供电流。 通过第一触发器（42）或第二触发器（43）将采样的输入电压交替地提供给可切换电流源（41）。 一个触发器对输入电压进行采样，而另一个触发器提供用于启用和禁用可切换电流源（41）的先前采样输入电压。 在输出电压改变到耦合到电流源（53）的晶体管（51）之后的预定时间内，开关（46,47）耦合第一或第二触发器（42,43）的输出电压。

    Comparator circuit and method thereof
    35.
    发明授权
    Comparator circuit and method thereof 失效
    比较器电路及其方法

    公开(公告)号：US5525920A

    公开(公告)日：1996-06-11

    申请号：US431965

    申请日：1995-05-01

    申请人： Patrick L. Rakers ,  Douglas A. Garrity

    发明人： Patrick L. Rakers ,  Douglas A. Garrity

    IPC分类号： H03K5/24 ,  H03K5/22

    CPC分类号： H03K5/2472

    摘要： Comparator circuit (72) samples a differential input signal at switched capacitor circuit (100). The input signal is stored across capacitors (128, 130, 132, 134). Reference voltages are subtracted from the input signal to produce a difference signal. The difference is compared to a mid-supply reference VMID, and an amplified representation of the signal is produced at the output of differential gain stage (136). Latching output stage (138) uses feedback circuits (204, 211 and 202, 208) to process the amplified signal and to produce a rail to rail representation of the amplified signal at the inputs (146, 148) of SR latch (140). The feedback circuit also powers-down the output stage after processing the amplified signal. Buffer circuits (205, 213 and 214, 212) allow a new signal to be processed by capacitor circuit (100) while the previous signal is being stored in the SR latch.

    摘要翻译： 比较器电路（72）在开关电容器电路（100）处采样差分输入信号。 输入信号存储在电容器（128,130,132,134）之间。 从输入信号中减去参考电压以产生差分信号。 将差值与中间电源参考VMID进行比较，并且在差分增益级（136）的输出处产生信号的放大表示。 锁存输出级（138）使用反馈电路（204,211和202,208）来处理放大的信号并且在SR锁存器（140）的输入端（146,148）处产生放大信号的轨至轨表示。 反馈电路在处理放大信号之后还对输出级进行掉电。 当先前的信号被存储在SR锁存器中时，缓冲电路（205,213和214,212）允许由电容器电路（100）处理新的信号。