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31.发明授权公开(公告)号：US07840757B2
公开(公告)日：2010-11-23
申请号：US10901600
申请日：2004-07-29
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.
摘要翻译： 具有直接更新诸如中央处理单元（CPU）或图形处理单元（GPU）的处理器的高速缓存（例如，主要L1高速缓存）存储器的计算机系统。 专用地址保留给高速存储器。 涉及这些保留地址的存储器访问请求直接路由到高速存储器。 不涉及这些保留地址的存储器访问请求被路由到处理器外部的存储器。
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公开(公告)号：US20090201302A1
公开(公告)日：2009-08-13
申请号：US12029647
申请日：2008-02-12
IPC分类号： G06F15/16
CPC分类号： G06T1/20
摘要： Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.
摘要翻译： 包括在芯片上的图形渲染（“NOC”），包括在几何处理器中接收要呈现的对象的表示; 通过几何处理器将对象的表示转换成二维原语; 由所述几何处理器将所述原语发送到所述多个扫描转换器; 由扫描转换器将原语转换成片段，每个片段包括像素的一个或多个部分; 对于每个片段：由扫描转换器根据排序规则选择片段以处理片段的像素处理器; 由扫描转换器向像素处理器发送片段; 以及由所述像素处理器处理所述片段以产生用于图像的像素。
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公开(公告)号：US20090125706A1
公开(公告)日：2009-05-14
申请号：US11936873
申请日：2007-11-08
IPC分类号： G06F9/38
CPC分类号： G06F9/5038 , G06F9/30047 , G06F9/3851 , G06F9/3885 , G06F15/7825 , G06F15/8053 , G06F2209/5017
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器， 其中每个存储器通信控制器控制IP块和存储器之间的通信以及控制通过路由器进行IP间块通信的每个网络接口控制器，NOC还包括被分段成阶段的计算机软件应用，每个级包括计算机程序的可灵活配置的模块 由阶段ID标识的指令，每个阶段在IP块上的执行线程上执行。
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公开(公告)号：US08392664B2
公开(公告)日：2013-03-05
申请号：US12118017
申请日：2008-05-09
CPC分类号： G06F12/126
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; and at least one IP block also including a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the cache controlled by a cache controller having a cache line replacement policy, the cache controller configured to lock segments of the cache, the computer processor configured to store thread-private data in main memory off the IP block, the computer processor further configured to store thread-private data on a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller's replacement policy, the segment further locked against write-through to main memory.
摘要翻译： 包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器的片上网络（NOC） 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 以及至少一个IP块，其还包括计算机处理器和包括IP块上的高速本地存储器的L1，直通数据高速缓存，由具有高速缓存行替换策略的高速缓存控制器控制的高速缓存，高速缓存控制器被配置为锁定 所述计算机处理器被配置为将主存储器中的线程专用数据存储在所述IP块之外，所述计算机处理器还被配置为将线程专用数据存储在所述L1数据高速缓存的段上，所述段被锁定以防止在高速缓存 错过了缓存控制器的替换策略，该段进一步锁定到主内存的写入。
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公开(公告)号：US08018466B2
公开(公告)日：2011-09-13
申请号：US12029647
申请日：2008-02-12
CPC分类号： G06T1/20
摘要： Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.
摘要翻译： 包括在芯片上的图形渲染（“NOC”），包括在几何处理器中接收要呈现的对象的表示; 通过几何处理器将对象的表示转换成二维原语; 由所述几何处理器将所述原语发送到所述多个扫描转换器; 由扫描转换器将原语转换成片段，每个片段包括像素的一个或多个部分; 对于每个片段：由扫描转换器根据排序规则选择片段以处理片段的像素处理器; 由扫描转换器向像素处理器发送片段; 以及由所述像素处理器处理所述片段以产生用于图像的像素。
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36.发明授权Network on chip with a low latency, high bandwidth application messaging interconnect 有权具有低延迟，高带宽应用消息互连的片上网络公开(公告)号：US07913010B2
公开(公告)日：2011-03-22
申请号：US12031733
申请日：2008-02-15
CPC分类号： G06F13/4027
摘要： A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); each IP block adapted to the data communications bus through a memory communications controller and a bus interface controller; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between an IP block and memory; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between one of the IP blocks and other IP blocks; each IP block adapted to the data communications bus by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译： 片上网络（NOC）和NOC数据处理方法，NOC包括集成处理器（IP）块，数据通信总线（110），存储器通信控制器（106）和总线接口控制器 108）; 每个IP块通过存储器通信控制器和总线接口控制器适应于数据通信总线; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和存储器之间的存储器寻址通信; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和其它IP块之一之间的存储器寻址通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应数据通信总线。
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公开(公告)号：US20100070714A1
公开(公告)日：2010-03-18
申请号：US12233180
申请日：2008-09-18
IPC分类号： G06F12/08 , G06F15/167
CPC分类号： G06F12/0842 , G06F12/126 , G06F15/7825
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, a multiplicity of computer processors, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器， 计算机处理器的多样性，每个计算机处理器实现多个硬件执行线程; 和计算机存储器，计算机存储器以页面组织并且可操作地耦合到一个或多个计算机处理器，该计算机存储器包括集合关联高速缓存，该高速缓存包括以集合组织的高速缓存方式，高速缓存在执行的硬件线程之间共享 计算机存储器的每一页被限制用于通过一类替换向量的一个替换向量到高速缓存的特定方式进行高速缓存，存储器的每一页被进一步限制用于通过替换向量分类的一个或多个位进行高速缓存到特定的一组方式 缓存。
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公开(公告)号：US20090282211A1
公开(公告)日：2009-11-12
申请号：US12117906
申请日：2008-05-09
IPC分类号： G06F12/02
CPC分类号： G06F12/1483 , G06F15/7825
摘要： Data processing with a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, including: organizing the network into partitions; assigning all IP blocks of a partition a partition identifier (‘partition ID’) that uniquely identifies for an IP block a particular partition in which the IP block is included; establishing one or more permissions tables associating partition IDs with sources and destinations of data communications on the NOC, each record in the permissions tables representing a restriction on data communications on the NOC; executing one or more applications on one or more of the partitions, including transmitting data communications messages among IP blocks and between IP blocks and memory, each data communications message including a partition ID of a sender of the data communications message; and controlling data communications among the partitions in dependence upon the permissions tables and the partition IDs.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”）的数据处理，包括：将网络组织成分区; 为分区的所有IP块分配一个分区标识符（“分区ID”），其为IP块唯一地标识其中包括IP块的特定分区; 建立将分区ID与NOC上的数据通信的源和目的地相关联的一个或多个许可表，权限表中的每个记录表示对NOC上的数据通信的限制; 在一个或多个分区上执行一个或多个应用，包括在IP块之间以及IP块和存储器之间传送数据通信消息，每个数据通信消息包括数据通信消息的发送者的分区ID; 以及根据权限表和分区ID控制分区之间的数据通信。
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公开(公告)号：US20090282197A1
公开(公告)日：2009-11-12
申请号：US12118017
申请日：2008-05-09
IPC分类号： G06F12/08
CPC分类号： G06F12/126
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; and at least one IP block also including a computer processor and an L1, write-through data cache comprising high speed local memory on the IP block, the cache controlled by a cache controller having a cache line replacement policy, the cache controller configured to lock segments of the cache, the computer processor configured to store thread-private data in main memory off the IP block, the computer processor further configured to store thread-private data on a segment of the L1 data cache, the segment locked against replacement upon cache misses under the cache controller's replacement policy, the segment further locked against write-through to main memory.
摘要翻译： 片上网络（“NOC”）包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 以及至少一个IP块，其还包括计算机处理器和包括IP块上的高速本地存储器的L1，直通数据高速缓存，由具有高速缓存行替换策略的高速缓存控制器控制的高速缓存，高速缓存控制器被配置为锁定 所述计算机处理器被配置为将主存储器中的线程专用数据存储在所述IP块之外，所述计算机处理器还被配置为将线程专用数据存储在所述L1数据高速缓存的段上，所述段被锁定以防止在高速缓存 错过了缓存控制器的替换策略，该段进一步锁定到主内存的写入。
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40.发明申请公开(公告)号：US20090187716A1
公开(公告)日：2009-07-23
申请号：US12015975
申请日：2008-01-17
IPC分类号： G06F12/08
CPC分类号： G06F12/0833
摘要： A network on chip (‘NOC’) that maintains cache coherency, the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, at least one memory communications controller further comprising a cache coherency controller each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.
摘要翻译： 一种保持高速缓存一致性的网络芯片（NOC），NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器适应于路由器， 网络接口控制器，至少一个存储器通信控制器，其还包括高速缓存一致性控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器，其中所述存储器通信控制器被配置 执行存储器访问指令并被配置为确定由存储器访问指令寻址的高速缓存行的状态，高速缓存行的状态是共享的，排他的或无效的之一; 所述存储器通信控制器被配置为如果所述高速缓存行的状态被共享，则向所述NOC的多个IP块广播无效命令; 以及所述存储器通信控制器被配置为仅当所述高速缓存行的状态是排他性时，将无效命令仅发送到控制高速缓存行存储的高速缓存的IP块。
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