公开(公告)号：US06557021B1

公开(公告)日：2003-04-29

申请号：US09527653

申请日：2000-03-17

申请人： Jeffrey S. Brooks ,  James S. Blomgren

发明人： Jeffrey S. Brooks ,  James S. Blomgren

IPC分类号： G06F738

CPC分类号： G06F7/49947 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/5443

摘要： A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One embodiment of the present invention includes four logic levels, implemented in N-NARY logic. In the first three logic levels, propagation information is gathered for preselected bit groups from the coarse and medium shift output of the normalizer as those results become available. In the fourth level, an incremented, normalized intermediate single-precision or double-precision mantissa result is produced by combining fine shift output bit values with propagation information for the appropriate top bit group, middle bit group, and bottom bit group. The appropriate bit groups are determined by examining the value of the fine shift select signal.

摘要翻译： 公开了一种在中间结果正规化的同时在浮点算术系统中执行中间结果的预期舍入的方法和装置。 本发明的一个实施例包括在N-NARY逻辑中实现的四个逻辑电平。 在前三个逻辑电平中，当这些结果变得可用时，从归一化器的粗中移位输出收集预选位组的传播信息。 在第四级中，通过将精细位移输出位值与适当的顶部位组，中间位组和底部位组的传播信息组合，产生递增的标准化中间单精度或双精度尾数结果。 通过检查精细位移选择信号的值来确定适当的位组。

公开(公告)号：US06460134B1

公开(公告)日：2002-10-01

申请号：US09181406

申请日：1998-10-28

申请人： James S. Blomgren ,  Terence M. Potter ,  Jeffrey S. Brooks

发明人： James S. Blomgren ,  Terence M. Potter ,  Jeffrey S. Brooks

IPC分类号： G06F930

CPC分类号： H03K19/0963 ,  G06F1/08 ,  G06F7/48 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/3869 ,  G06F2207/3888 ,  G11C7/1006 ,  G11C11/56 ,  H03K19/00346

摘要： The present invention comprises a method and apparatus for a pipeline of functional units with a late pipe functional unit that executes instructions without stalling until the result is available. The present invention comprises one or more earlier functional units coupled to a late pipe functional unit. The late pipe functional unit does not begin executing instructions until all of the input operands are or will be available for execution so that the late pipe functional unit will execute instructions without stalling until the result will be available in a fixed number of cycles. The present invention further comprises a late pipe functional unit that may comprise a floating point unit, a graphics unit, or an enhanced floating point unit. And finally, the late pipe functional unit is non-stalling and or is non-cancelable.

摘要翻译： 本发明包括一种具有后期管道功能单元的功能单元流水线的方法和装置，其执行指令而不停顿，直到结果可用。 本发明包括一个或多个耦合到延迟管功能单元的功能单元。 所有后期管道功能单元都不会开始执行指令，直到所有的输入操作数都可以执行或者可以执行，以便后期管道功能单元执行指令而不停顿，直到结果以固定的循环数可用。 本发明还包括可以包括浮点单元，图形单元或增强型浮点单元的后期管道功能单元。 最后，后期管道功能单元不停滞，或不可取消。

公开(公告)号：US5787610A

公开(公告)日：1998-08-04

申请号：US861579

申请日：1997-05-22

申请人： Jeffrey S. Brooks

发明人： Jeffrey S. Brooks

IPC分类号： A43B7/14 ,  A43B7/22 ,  A43B7/32 ,  A43B13/12 ,  A43B13/18 ,  A43B13/41 ,  A43B17/10 ,  A43B13/14

CPC分类号： A43B7/141 ,  A43B1/0027 ,  A43B1/0045 ,  A43B13/12 ,  A43B13/187 ,  A43B13/41 ,  A43B17/102 ,  A43B3/0063 ,  A43B7/14 ,  A43B7/142 ,  A43B7/1425 ,  A43B7/1435 ,  A43B7/144 ,  A43B7/1445 ,  A43B7/22 ,  A43B7/32

摘要： Footwear comprising a sole formed from a first resilient material for attenuating the shock of impact to a wearer during running or walking, and a second material harder than the first material for providing firm support for a foot. The sole has heel, arch and toe sections, each of which have medial and lateral regions. The sole also has a forefoot section having a first region for supporting the first, second, third, fourth and fifth metatarsal heads of the foot, associated phalanges and metatarsal phalangeal joints, and the metatarsal necks associated with the fourth and fifth metatarsal heads, and a second region for supporting the metatarsal necks associated with the second and third metatarsal heads. The sole is formed so that the first resilient material is positioned in the lateral region of the heel section, the lateral region of the arch section, and the first region of the forefoot section, and so that the second harder material is positioned in the medial region of the arch section, and the second region of the forefoot section.

公开(公告)号：US5678003A

公开(公告)日：1997-10-14

申请号：US546368

申请日：1995-10-20

申请人： Jeffrey S. Brooks

发明人： Jeffrey S. Brooks

IPC分类号： G06F11/36 ,  G06F11/00

CPC分类号： G06F11/3664 ,  G06F11/3636

摘要： A multiprocessor system provides for a restartable stop condition that is fast and easily implemented. The multiprocessor system includes a plurality of processors. Each of the processors includes a bidirectional stop pin, which normally when asserted indicates that an error has been detected. Each of the plurality of processors also includes a scan port. The plurality of processors in the multiprocessor system are coupled together via their respective stop pins. By switching the stop pins to a different mode whereby an assertion of the pin causes the receiving processor to enter a restartable stop condition as a result of a restartable stop condition being achieved by the driving processor, the multiprocessor system can be quickly stopped. The restartable system stop technique when implemented utilizing a plurality of processors in which each of the processors include this stop pin provides both a straightforward and fast method for stopping a multiprocessor system in a restartable manner following the occurrence of any particular event. This commonly includes an instruction address breakpoint, single instruction step, data address breakpoint, or specific JTAG instruction. Memory coherency in the multiprocessor system is maintained throughout, such that functional clocks may be stopped, the machine state observed and restored in a non-destructive manner via scan, and functional clocks and code execution can then be restarted.

摘要翻译： 多处理器系统提供快速，轻松实现的可重启停止条件。 多处理器系统包括多个处理器。 每个处理器包括一个双向停止引脚，通常当断言指示已经检测到错误时。 多个处理器中的每一个还包括扫描端口。 多处理器系统中的多个处理器通过它们各自的停止引脚耦合在一起。 通过将停止引脚切换到不同的模式，由于由驱动处理器实现的可重启停止条件的结果，引脚的断言使得接收处理器进入可重启停止状态，因此可以快速停止多处理器系统。 当利用多个处理器来实现可重新启动的系统停止技术，其中每个处理器包括该停止引脚提供在发生任何特定事件之后以可重启的方式停止多处理器系统的直接和快速的方法。 这通常包括指令地址断点，单指令步，数据地址断点或特定的JTAG指令。 多处理器系统中的存储器一致性被维持，使得可以停止功能时钟，通过扫描以非破坏性的方式观察和恢复机器状态，然后可以重新启动功能时钟和代码执行。

公开(公告)号：US07798339B2

公开(公告)日：2010-09-21

申请号：US11668215

申请日：2007-01-29

申请人： Jeffrey S. Brooks ,  Gregory A. Wirtel

发明人： Jeffrey S. Brooks ,  Gregory A. Wirtel

IPC分类号： A47H1/00

CPC分类号： G11B33/02

摘要： In general, this invention is directed to a rail and slider system having residential and commercial organizational applications. In one aspect, the system comprises at least one rail and a slider mounted on the rail for sliding movement along the rail. The rail and slider have teeth which releasably engage with one another for locking the slider at selected positions along the rail. A spring device on the slider urges the slider toward a locked position. The slider is manually movable against the urging of the spring device from its locked position to an unlocked position in which the teeth on the arms and the tracks are disengaged to permit sliding movement of the slider along the rail to a different selected position. Various items can be attached to the slider, e.g., a funnel-shaped holder and shelf bracket. In other aspects, the slider is configured for snap-mounting on the rail, and a kit is provided including at least two rails and sliders, and a template for mounting the rails on a surface such that the rails are in proper position relative to one another.

摘要翻译： 通常，本发明涉及一种具有住宅和商业组织应用的轨道和滑块系统。 在一个方面，该系统包括至少一个轨道和安装在轨道上的滑块，用于沿轨道滑动。 轨道和滑块具有可释放地彼此接合的齿，用于将滑块锁定在沿着轨道的选定位置处。 滑块上的弹簧装置将滑块推向锁定位置。 滑动器可以克服弹簧装置从其锁定位置的推动手动地移动到解锁位置，在该位置，臂和轨道上的齿被分离，以允许滑块沿着轨道滑动到不同的选定位置。 可以将各种物品附接到滑块，例如漏斗状保持器和搁架支架。 在其它方面，滑动件构造成用于卡扣安装在轨道上，并且提供了包括至少两个轨道和滑块的套件，以及用于将轨道安装在表面上的模板，使得轨道相对于一个位于适当位置 另一个。

公开(公告)号：US07774393B1

公开(公告)日：2010-08-10

申请号：US10881187

申请日：2004-06-30

申请人： Jeffrey S. Brooks ,  Sadar U. Ahmed

发明人： Jeffrey S. Brooks ,  Sadar U. Ahmed

IPC分类号： G06F7/00

CPC分类号： H03M7/24

摘要： An apparatus and method for integer to floating-point format conversion. A processor may include an adder configured to perform addition of respective mantissas of two floating-point operands to produce a sum, where a smaller-exponent one of the floating-point operands has a respective exponent less than or equal to a respective exponent of a larger-exponent one of the floating-point operands. The processor may further include an alignment shifter coupled to the adder and configured, in a first mode of operation, to align the floating-point operands prior to the addition by shifting the respective mantissa of the smaller-exponent operand towards a least-significant bit position. The alignment shifter may be further configured, in a second mode of operation, to normalize an integer operand by shifting the integer operand towards a most-significant bit position. The second mode of operation may be active during execution of an instruction to convert the integer operand to floating-point format.

摘要翻译： 一种用于整数到浮点格式转换的装置和方法。 处理器可以包括加法器，其被配置为执行两个浮点操作数的相应尾数的相加以产生和，其中较小指数的浮点操作数具有小于或等于相应指数的相应指数 较大指数的浮点操作数之一。 处理器还可以包括对准移位器，其耦合到加法器并且在第一操作模式下被配置为通过将较小指数操作数的相应尾数偏移到最低有效位来对准在加法之前的浮点操作数 位置。 在第二操作模式中，对准移位器可进一步配置为通过将整数操作数移向最高有效位位置来对整数操作数进行归一化。 在执行将整数操作数转换为浮点格式的指令期间，第二操作模式可以是活动的。

公开(公告)号：US06499044B1

公开(公告)日：2002-12-24

申请号：US09546412

申请日：2000-04-10

申请人： Jeffrey S. Brooks ,  James S. Blomgren ,  David E. Kreml

发明人： Jeffrey S. Brooks ,  James S. Blomgren ,  David E. Kreml

IPC分类号： G06F750

CPC分类号： G06F7/74 ,  G06F7/49 ,  G06F2207/3832

摘要： An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of N-NARY logic, wherein the first logic level generates dit-level propagate-generate-zero (PGZ) patterns and carry out signals from the input dits of the adder operands. The second logic level produces a find-zero and a find-one output signal for each two-dit group of the adder result by combining PGZ patterns for the two dits within the group with the carry-out signal from the dit immediately preceding the two-dit group. The third logic level combines find-zero and find-one output signals for each two-dit group to produce find-one and find-zero coarse and medium shift select signals.

摘要翻译： 公开了一种能够与浮点加法器并行操作的有效率的前导零/前导预测器（LZA）。 在一个实施例中，LZA可以在N-NARY逻辑的三个级别中实现，其中第一逻辑电平产生二进制传播生成零（PGZ）模式，并且从加法器操作数的输入位执行信号。 第二逻辑电平通过将组内的两个位数的PGZ模式与来自紧接在两者之间的dit的进位信号组合来产生加法器结果的每个二位组的查找零和寻找一个输出信号 -dit组。 第三逻辑电平将寻找零和找出一个输出信号组合在一起，以产生找到一个和查找零的粗和中移位选择信号。

公开(公告)号：US6151615A

公开(公告)日：2000-11-21

申请号：US120776

申请日：1998-07-22

申请人： Jeffrey S. Brooks ,  James S. Blomgren

发明人： Jeffrey S. Brooks ,  James S. Blomgren

IPC分类号： G06F5/01 ,  G06F7/57 ,  G06F7/38

CPC分类号： G06F5/012 ,  G06F7/483 ,  G06F7/49957

摘要： The present invention describes an apparatus and method that formats the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization and rounding of the intermediate fraction result has occurred. The output fraction is formatted using all or some of the bits from the output of either the rounder circuit or the normalizer circuit.

摘要翻译： 本发明描述了一种设备和方法，其格式化ANSI / IEEE 754-1985浮点算术运算的输出分数结果，其中并行归一化和中间分数结果的舍入已经发生。 输出分数使用来自四舍五入电路或归一化电路的输出的全部或部分位进行格式化。

公开(公告)号：US06041524A

公开(公告)日：2000-03-28

申请号：US166357

申请日：1998-10-05

申请人： Jeffrey S. Brooks

发明人： Jeffrey S. Brooks

IPC分类号： A43B7/16 ,  A43B13/41 ,  A43B7/14 ,  A43B23/28

CPC分类号： A43B7/144 ,  A43B13/41 ,  A43B7/16

摘要： Footwear including a sole having a front and a back for supporting a bottom of a foot. A heel cup at the back of the sole receives and supports a heel of the foot. The heel cup has a bottom for further supporting the bottom of the foot and a side wall extending up from the bottom. The side wall has a generally concave rear section for receiving and supporting the back of the heel and opposite side sections extending forward from the rear section. The recess in the rear section of the side wall of the heel cup is offset laterally from a longitudinal central vertical plane of the heel cup. The recess is sized for accommodating the rearwardly protruding lateral posterior portion of the calcaneus of the foot.

摘要翻译： 鞋类包括具有用于支撑脚底部的前部和后部的鞋底。 在鞋底后部的脚跟接收并支撑足部脚跟。 脚跟杯具有用于进一步支撑脚的底部的底部和从底部向上延伸的侧壁。 侧壁具有大致凹入的后部，用于接收和支撑后跟的后部和从后部向前延伸的相对侧部。 后跟杯的侧壁的后部中的凹部从跟部杯的纵向中心垂直平面侧向偏移。 凹部的尺寸适于容纳脚的跟骨的向后突出的侧向后部。

公开(公告)号：US08534079B2

公开(公告)日：2013-09-17

申请号：US12726910

申请日：2010-03-18

申请人： Jeffrey S. Brooks

发明人： Jeffrey S. Brooks

IPC分类号： F25B19/00

CPC分类号： F25D3/105 ,  F25D21/04 ,  F25D21/10 ,  F25D29/001 ,  F25D2700/12

摘要： A freezer that uses liquid cryogen as a refrigerant includes an inner vessel defining a storage chamber and an outer jacket generally surrounding the inner vessel so that an insulation space is defined there between. A heat exchanger is positioned in a top portion of the storage chamber and has an inlet in communication with a supply of the liquid cryogen refrigerant so that the liquid cryogen refrigerant selectively flows through the heat exchanger to cool the storage chamber while being vaporized. A purge line is in communication with the outlet of the heat exchanger and includes a purge outlet positioned over the exterior of the heat exchanger. A purge valve is positioned within the purge line so that the vaporized liquid cryogen from the heat exchanger is selectively directed to the exterior of the heat exchanger to reduce ice formation on the heat exchanger.

摘要翻译： 使用液体冷冻剂作为制冷剂的冷冻机包括限定储存室的内部容器和通常围绕内部容器的外部护套，从而在其间限定绝缘空间。 热交换器位于储存室的顶部，并且具有与液体致冷剂制冷剂供应源连通的入口，使得液体制冷剂制冷剂选择性地流过热交换器以在蒸发时冷却储存室。 净化线与热交换器的出口连通，并且包括位于热交换器外部的净化出口。 净化阀位于净化管线内，使得来自热交换器的蒸发的液体冷冻剂选择性地导向热交换器的外部，以减少热交换器上的冰层形成。