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    Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants
    32.
    发明授权
    Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants 有权
    半导体结构的配置和制造，其中场效应晶体管的源极和漏极扩展由不同掺杂剂定义

    公开(公告)号：US08304320B2

    公开(公告)日：2012-11-06

    申请号：US13100192

    申请日：2011-05-03

    Applicant: Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

    Inventor： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

    IPC: H01L21/336 ,  H01L21/8238

    CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/66659

    Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

    Abstract translation: 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括与主要部分横向连续并在栅电极下方横向延伸的主要部分（240M或242M）和更轻掺杂的侧向延伸部（240E或242E）。 沿着上半导体表面终止沟道区的横向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源极的横向延伸比起漏极的横向延伸稍微掺杂，并且由原子量较高的掺杂剂限定。

    STATIC INDUCTION TRANSISTOR WITH DIELECTRIC CARRIER SEPARATION LAYER
    34.
    发明申请
    STATIC INDUCTION TRANSISTOR WITH DIELECTRIC CARRIER SEPARATION LAYER 审中-公开
    具有介质载体分离层的静态感应晶体管

    公开(公告)号：US20120139013A1

    公开(公告)日：2012-06-07

    申请号：US12959736

    申请日：2010-12-03

    Applicant: Sandeep Bahl ,  Constantin Bulucea

    Inventor： Sandeep Bahl ,  Constantin Bulucea

    IPC: H01L29/808 ,  H01L21/337

    CPC classification number: H01L29/7722 ,  H01L27/085

    Abstract: A static induction transistor comprising: a region of semiconductor material having a first conductivity type; at least two spaced-apart gate regions formed in the region of semiconductor material, the gate regions having a second conductivity type that is opposite to the first conductivity type; at least one source region having the first conductivity type formed in the region of semiconductor material between the spaced-apart gate regions; a drain region having the first conductivity type formed in the region of semiconductor and spaced-apart from the source region to define a channel region therebetween; and a dielectric carrier separation layer formed at the periphery of the gate regions.

    Abstract translation: 一种静电感应晶体管，包括：具有第一导电类型的半导体材料区域; 形成在所述半导体材料区域中的至少两个间隔开的栅极区域，所述栅极区域具有与所述第一导电类型相反的第二导电类型; 在所述间隔开的栅极区域之间的半导体材料的区域中形成具有第一导电类型的至少一个源极区域; 具有第一导电类型的漏极区，形成在半导体区域中并与源极区间隔开以在其间限定沟道区; 以及形成在栅极区域的周边的介电载体分离层。

    Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length
    35.
    发明授权
    Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length 有权
    具有减小的结电容和阈值电压的场效应晶体管的制造随着沟道长度的增加而减小

    公开(公告)号：US07879669B1

    公开(公告)日：2011-02-01

    申请号：US11527265

    申请日：2006-09-25

    Applicant: Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

    Inventor： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

    IPC: H01L29/78

    CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

    Abstract: At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 μm greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 μm greater than LC.

    Abstract translation: 提供增强型绝缘栅场效应晶体管（120或122）的至少一个源极/漏极区（140,142,160或162）具有渐变结特征以减小结电容，从而提高开关速度。 每个分级接点源极/漏极区域包含主要部分（140M，142M，160M或162M）和在主要部分下面并垂直连续的较轻掺杂的下部分（140L，142L，160L或162L）。 在通道长度为LC时，在相同布局前制造工艺条件下制造的一组这样的晶体管的阈值电压的幅度达到最大绝对值VTAM至少为0.03 当沟道长度比LC大约0.3μm时，小于VTAM的伏特，并且当沟道长度大于LC时大约1.0μm时，随着沟道长度的增加而实质上减小。

    Semiconductor structure utilizing empty and filled wells
    36.
    发明授权
    Semiconductor structure utilizing empty and filled wells 有权
    利用空和填充井的半导体结构

    公开(公告)号：US07863681B1

    公开(公告)日：2011-01-04

    申请号：US12545024

    申请日：2009-08-20

    Applicant: Constantin Bulucea

    Inventor： Constantin Bulucea

    IPC: H01L27/088

    CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

    Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

    Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
    37.
    发明授权
    Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications 有权
    具有特别适用于模拟应用的场效应晶体管的半导体架构的制造

    公开(公告)号：US07838369B2

    公开(公告)日：2010-11-23

    申请号：US11981355

    申请日：2007-10-31

    Applicant: Constantin Bulucea

    Inventor： Constantin Bulucea

    IPC: H01L27/088

    CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material is preferably provided with a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

    Abstract translation: 制造绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480） 以便具有低于其源极/漏极区的一个（104或264）的低破坏垂直掺杂剂轮廓，用于减小沿着该源极/漏极区与邻接主体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的物体 - 物质位置之前至少增加10倍，不超过上部的10倍 半导体表面比该源/漏区。 主体材料优选地设置有沿着另一个源极/漏极区（102或262）设置的更加重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

    Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor
    38.
    发明申请
    Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor 审中-公开
    具有扩展漏极场效应晶体管的半导体结构的配置和制造

    公开(公告)号：US20100244152A1

    公开(公告)日：2010-09-30

    申请号：US12382976

    申请日：2009-03-27

    Applicant: Sandeep R. Bahl ,  Constantin Bulucea ,  William D. French

    Inventor： Sandeep R. Bahl ,  Constantin Bulucea ,  William D. French

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

    Abstract: An extended-drain insulated-gate field-effect transistor (104 or 106) contains first and second source/drain zones 324 and 184B or 364 and 186B) laterally separated by a channel (322 or 362) zone constituted by part of a first well region (184A or 186A). A gate dielectric layer (344 or 384) overlies the channel zone. A gate electrode (346 or 386) overlies the gate dielectric layer above the channel zone. The first source/drain zone is normally the source. The second S/D zone, normally the drain, is constituted with a second well region (184B or 186B). A well-separating portion 186A or 186B/212U) of the semiconductor body extends between the well regions and is more lightly doped than each well region. The configuration of the well regions cause the maximum electric field in the IGFET's portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other. The IGFET's operating characteristics are stable with operational time.

    Abstract translation: 扩展漏极绝缘栅场效应晶体管（104或106）包含由第一阱的一部分构成的沟道（322或362）区域横向隔开的第一和第二源/漏区324和184B或364和186B， 区域（184A或186A）。 栅极电介质层（344或384）覆盖在沟道区上。 栅电极（346或386）覆盖沟道区上方的栅介质层。 第一个源/漏区通常是源。 第二S / D区（通常为漏极）由第二阱区（184B或186B）构成。 半导体本体的阱分离部分186A或186B / 212U）在阱区之间延伸，并且比每个阱区域轻掺杂。 阱区域的配置导致半导体本体的IGFET的部分中的最大电场远低于上半导体表面，通常处于或接近阱区彼此最接近的位置。 IGFET的运行特性在运行时间稳定。

    Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics
    39.
    发明授权
    Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics 有权
    其中类似极性绝缘栅场效应晶体管具有多个垂直体掺杂浓度最大值和不同晕圈特征的半导体结构

    公开(公告)号：US07701005B1

    公开(公告)日：2010-04-20

    申请号：US11974751

    申请日：2007-10-15

    Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

    Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

    IPC: H01L29/80

    CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

    Abstract: Each of a pair of differently configured like-polarity insulated-gate field-effect transistors (40 or 42 and 240 or 242) in a semiconductor structure has a channel zone of semiconductor body material, a gate dielectric layer overlying the channel zone, and a gate electrode overlying the gate dielectric layer. For each transistor, the net dopant concentration of the body material reaches multiple local subsurface maxima below a channel surface depletion region and below largely all gate-electrode material overlying the channel zone. The transistors have source/drain zones (60 or 80) of opposite conductivity type to, and halo pocket portions of the same conductivity type as, the body material. One pocket portion (100/102 or 104) extends along both source/drain zones of one of the transistors. Another pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

    Abstract translation: 半导体结构中的一对不同构造的相同极性的绝缘栅场效应晶体管（40或42和240或242）中的每一个具有半导体主体材料的沟道区，覆盖沟道区的栅介质层和 覆盖栅介电层的栅电极。 对于每个晶体管，主体材料的净掺杂剂浓度在沟道表面耗尽区下方达到多个局部地下极大值，并且大部分覆盖在沟道区上方的所有栅电极材料。 晶体管具有与主体材料相同的导电类型的源极/漏极区域（60或80）以及与主体材料相同的导电类型的卤素口袋部分。 一个口袋部分（100/102或104）沿着一个晶体管的源极/漏极区域延伸。 另一个口袋部分（244或246）沿着另一个晶体管的源极/漏极区域中的一个较大地延伸，使得它是不对称的。

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