公开(公告)号：US20120139013A1

公开(公告)日：2012-06-07

申请号：US12959736

申请日：2010-12-03

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/808 ,  H01L21/337

CPC classification number: H01L29/7722 ,  H01L27/085

Abstract: A static induction transistor comprising: a region of semiconductor material having a first conductivity type; at least two spaced-apart gate regions formed in the region of semiconductor material, the gate regions having a second conductivity type that is opposite to the first conductivity type; at least one source region having the first conductivity type formed in the region of semiconductor material between the spaced-apart gate regions; a drain region having the first conductivity type formed in the region of semiconductor and spaced-apart from the source region to define a channel region therebetween; and a dielectric carrier separation layer formed at the periphery of the gate regions.

Abstract translation: 一种静电感应晶体管，包括：具有第一导电类型的半导体材料区域; 形成在所述半导体材料区域中的至少两个间隔开的栅极区域，所述栅极区域具有与所述第一导电类型相反的第二导电类型; 在所述间隔开的栅极区域之间的半导体材料的区域中形成具有第一导电类型的至少一个源极区域; 具有第一导电类型的漏极区，形成在半导体区域中并与源极区间隔开以在其间限定沟道区; 以及形成在栅极区域的周边的介电载体分离层。

公开(公告)号：US08502273B2

公开(公告)日：2013-08-06

申请号：US12908458

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/778 ,  H01L21/338

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

Abstract: The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.

Abstract translation: 通过在p型Si衬底中形成n阱以直接位于III-NHEMT族金属漏极区的下方，在p型Si衬底上的III-N HEMT组的缓冲击穿显着增加。 n阱形成在击穿期间变得反向偏置的p-n结，从而通过p-n结的反向偏置击穿电压增加缓冲器击穿，并允许衬底接地。 III-N型HEMT的缓冲层也可以注入与p-n结对准的n型和p型掺杂剂，以最小化衬底和缓冲层之间的接合处的任何漏电流。

公开(公告)号：US08513703B2

公开(公告)日：2013-08-20

申请号：US12908514

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L21/338 ,  H01L29/778

CPC classification number: H01L29/0661 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.

Abstract translation: 组III-N HEMT的Si衬底形成为限定将Si衬底的上部区域与Si衬底的下部区域电隔离的p-n结的层。 结果，Si衬底的上部区域可以电浮动，从而获得全缓冲击穿电压，而Si衬底的下部区域可以通过导电环氧树脂附着到封装上，从而显着提高导热性 的III-N HEMT组，并且使不期望的浮动电压区域最小化。

公开(公告)号：US20120098036A1

公开(公告)日：2012-04-26

申请号：US12908514

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/0661 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.

Abstract translation: 组III-N HEMT的Si衬底形成为限定将Si衬底的上部区域与Si衬底的下部区域电隔离的p-n结的层。 结果，Si衬底的上部区域可以电浮动，从而获得全缓冲击穿电压，而Si衬底的下部区域可以通过导电环氧树脂附着到封装上，从而显着提高导热性 的III-N HEMT组，并且使不期望的浮动电压区域最小化。

公开(公告)号：US20120098035A1

公开(公告)日：2012-04-26

申请号：US12908458

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

Abstract: The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.

Abstract translation: 通过在p型Si衬底中形成n阱以直接位于III-NHEMT族金属漏极区的下方，在p型Si衬底上的III-N HEMT组的缓冲击穿显着增加。 n阱形成在击穿期间变得反向偏置的p-n结，从而通过p-n结的反向偏置击穿电压增加缓冲器击穿，并允许衬底接地。 III-N型HEMT的缓冲层也可以注入与p-n结对准的n型和p型掺杂剂，以最小化衬底和缓冲层之间的接合处的任何漏电流。

公开(公告)号：US08395212B2

公开(公告)日：2013-03-12

申请号：US13177552

申请日：2011-07-06

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US08377768B2

公开(公告)日：2013-02-19

申请号：US13293096

申请日：2011-11-09

Applicant: Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

Inventor： Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

IPC: H01L21/8238

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Abstract translation: 一组高性能类似极性的绝缘栅场效应晶体管（100,108,112,116,120和124或102,110,114,118,122和126）具有可选择地不同的侧向源 /漏极延伸，光晕口和栅介质厚度，适用于为模拟和/或数字应用提供各种晶体管的半导体制造平台。 每个晶体管具有一对源极/漏极区，栅极介电层和栅电极。 每个源极/漏极区域包括主要部分和更轻掺杂的横向延伸部分。 一个晶体管的一个源极/漏极区域的横向延伸比另一个晶体管的源极/漏极区域之一的横向延伸更深地掺杂或/并且在上部半导体表面之下更深地延伸。

公开(公告)号：US20100244151A1

公开(公告)日：2010-09-30

申请号：US12382974

申请日：2009-03-27

Applicant: William D. French ,  Constantin Bulucea

Inventor： William D. French ,  Constantin Bulucea

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (100W) has a source (980) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material normally extends largely along only the source so that the IGFET is an asymmetric device. The source has a main source portion (980M) and a more lightly doped lateral source extension (980E). The semiconductor dopant which defines the source reaches multiple local concentration maxima in defining the source extension. The procedure involved in defining the source extension with semiconductor dopant that reaches two such local concentration maxima enables source/drain extensions of mutually different characteristics for three insulated-gate field-effect transistors to be defined in only two source/drain-extension doping operations.

Abstract translation: 绝缘栅场效应晶体管（100W）具有由半导体主体的主体材料（180）的沟道区（244）横向隔开的源极（980）和漏极（242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 主体材料的更重掺杂的袋部分（250）通常沿着源极大部分地延伸，使得IGFET是非对称的装置。 源极具有主源部分（980M）和更轻掺杂的侧向源延伸部（980E）。 限定源极的半导体掺杂剂在限定源延伸时达到多个局部最大浓度。 用半导体掺杂剂定义达到两个这样的局部浓度最大值的源极扩展所涉及的过程使得三个绝缘栅场效应晶体管的源极/漏极扩展能够仅在两个源极/漏极 - 扩展掺杂操作中被定义。

公开(公告)号：US20100244150A1

公开(公告)日：2010-09-30

申请号：US12382972

申请日：2009-03-27

Applicant: Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

Inventor： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/66659

Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

Abstract translation: 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括与主要部分横向连续并在栅电极下方横向延伸的主要部分（240M或242M）和更轻掺杂的侧向延伸部（240E或242E）。 沿着上半导体表面终止沟道区的横向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源极的横向延伸比起漏极的横向延伸稍微掺杂，并且由原子量较高的掺杂剂限定。

公开(公告)号：US07700980B1

公开(公告)日：2010-04-20

申请号：US11975278

申请日：2007-10-17

Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L31/112

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: Each of a pair of like-polarity IGFETs (40 or 42 and 240 or 242) has a channel zone (64 or 84) situated in body material (50). Short-channel effects are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.4 μm deep into the body material. A pocket portion (100/102 or 104) extends along both source drain zones of one of the IGFETs. A pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other IGFET so that it is an asymmetrical device.

Abstract translation: 一对相同极性的IGFET（40或42和240或242）中的每一个具有位于主体材料（50）中的通道区（64或84）。 通过设置沟道区域中的净掺杂剂浓度以在IGFET的源极/漏极区域（60和62或80和82）之间的位置处纵向达到局部表面最小值并且通过布置净掺杂剂来缓解短沟道效应 在身体材料中的浓度达到局部地下最大超过0.1μm深的身体材料，但不超过0.4μm深入身体材料。 袋部分（100/102或104）沿着IGFET之一的两个源极漏极区延伸。 袋部分（244或246）沿着另一个IGFET的源极/漏极区域中的一个较大地延伸，使得它是不对称的装置。