公开(公告)号：US5388104A

公开(公告)日：1995-02-07

申请号：US813444

申请日：1991-12-26

申请人： Tsukasa Shirotori ,  Kazutaka Nogami

发明人： Tsukasa Shirotori ,  Kazutaka Nogami

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/28 ,  G11C29/56

CPC分类号： G11C29/28 ,  G11C29/02

摘要： A semiconductor integrated circuit includes a plurality of writable/readable memory blocks with different address spaces and an address decoder for selecting addresses of the memory blocks. The multiple memory blocks are permitted to share a part of addresses of the memory blocks in a test mode. The writing operation of one of the memory blocks that does not have the largest address space is disabled during a period in which address signals for commonly performing an address scan of individual memory blocks exceeds the address width of that memory block. It is therefore possible to permit a plurality of memory blocks with different address spaces mounted on the same chip to be tested with high precision and without additional burden on the generation of test vectors or on a BIST (built-in self test) test circuit.

摘要翻译： 半导体集成电路包括具有不同地址空间的多个可写/可读存储块和用于选择存储块地址的地址解码器。 允许多个存储器块在测试模式下共享存储器块的一部分地址。 在通常执行各个存储器块的地址扫描的地址信号超过该存储器块的地址宽度的时段期间禁止不具有最大地址空间的存储器块之一的写入操作。 因此，可以允许具有安装在同一芯片上的不同地址空间的多个存储块以高精度进行测试，并且不产生测试向量或BIST（内置自检）测试电路的额外负担。

公开(公告)号：US5175604A

公开(公告)日：1992-12-29

申请号：US681665

申请日：1991-04-08

申请人： Kazutaka Nogami

发明人： Kazutaka Nogami

IPC分类号： H01L29/78 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/412 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H03F3/45

CPC分类号： H01L27/108 ,  G11C11/4091 ,  G11C11/412 ,  H01L27/088 ,  Y10S257/919

摘要： A field-effect transistor device comprising a p-type silicon substrate, a pair of n-channel MOS transistors, and a wiring means connecting the MOS transistors. The first MOS transistor has a gate electrode provided above the substrate and extending in one direction, and two regions formed in the substrate, located on two opposing sides of the gate electrode, and serving as a source and a drain. The second MIS transistor has a gate electrode provided above the substrate and extending in said one direction, and two regions formed in the substrate, located on two opposing sides of this gate electrode, and serving as a source and a drain. The wiring means includes bit lines BL and BL which permit the source-drain paths of the first and second MIS transistors to be oriented in the same direction.

摘要翻译： 包括p型硅衬底，一对n沟道MOS晶体管和连接MOS晶体管的布线装置的场效应晶体管器件。 第一MOS晶体管具有设置在基板上并沿一个方向延伸的栅电极，以及形成在基板中的两个区域，位于栅电极的两个相对侧上，并用作源极和漏极。 第二MIS晶体管具有设置在基板上并沿所述一个方向延伸的栅电极，以及位于该栅电极的两个相对侧的基板中形成的两个区域，并用作源极和漏极。 布线装置包括允许第一和第二MIS晶体管的源极 - 漏极路径沿相同方向取向的位线BL和＆amp;上升和下降B。

公开(公告)号：US5073873A

公开(公告)日：1991-12-17

申请号：US439870

申请日：1989-11-21

申请人： Kazutaka Nogami

发明人： Kazutaka Nogami

IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C11/407 ,  G11C11/408 ,  H01L27/10

CPC分类号： G11C8/10

摘要： This invention is directed to a device to decode a row address by a row decoder thereafter to latch the decoded signal by a latch circuit, thus allowing the latched signal to drive a memory cell in a memory cell array. Since respective addresses are latched after decoded as stated above, no decode time is included in one cycle time and the cycle time is therefore shortened.