公开(公告)号：US20140040600A1

公开(公告)日：2014-02-06

申请号：US14113058

申请日：2012-04-10

申请人： Fumio Arakawa

发明人： Fumio Arakawa

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/30058 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/382

摘要： It is to provide a data processor which maintains compatibility with an existing instruction set such as a 16-bit fixed-length instruction set and in which an instruction code space is extended.In the data processor in which a combination of multiple specific instructions is prohibited, an instruction set is employed that additionally defines that prohibition combination pattern as a separate instruction. With respect to the prohibition combination pattern additionally defined as the separate instruction, for example, in order to make a definition in such a manner that an instruction dispatch mechanism for the instruction set that is present before the additional definition is used as is, the instruction to be additionally defined by the prohibition combination pattern is limited to an instruction type that is the same as the instruction defined only with a latter-half code of the instruction in a case of an instruction set in which the instruction set that is present before the additional definition includes a prefix code.

摘要翻译： 它提供一种数据处理器，其保持与诸如16位固定长度指令集的现有指令集的兼容性，并且其中指令代码空间被扩展。 在禁止多个特定指令的组合的数据处理器中，采用另外将禁止组合模式定义为单独指令的指令集。 对于另外定义为分离指令的禁止组合模式，例如为了进行定义，使得在附加定义之前存在的指令集的指令分派机制被使用，指令 另外由禁止组合模式定义的指令类型与仅在指令集的后半部分中定义的指令相同的指令类型，其中指令集的存在于指令集之前的指令集 附加定义包括前缀码。

公开(公告)号：US20100064119A1

公开(公告)日：2010-03-11

申请号：US12546809

申请日：2009-08-25

申请人： Fumio Arakawa

发明人： Fumio Arakawa

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30043 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3814 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3867

摘要： The present invention is directed to realize efficient issue of a superscalar instruction in an instruction set including an instruction with a prefix. A circuit is employed which retrieves an instruction of each instruction code type other than a prefix on the basis of a determination result of decoders for determining an instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant to instruction executing means. When an instruction of a target instruction code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target instruction code type as prefix code candidates. When an instruction of a target instruction code type cannot be detected at the rear end of the instruction units to be searched, the circuit outputs the instruction at the rear end as a prefix code candidate. When an instruction of a target instruction code type is detected at the head in the instruction code search, the circuit outputs the instruction code at the head.

摘要翻译： 本发明旨在实现包括具有前缀的指令的指令集中的超标量指令的有效问题。 使用电路，其基于用于确定指令代码类型的解码器的确定结果检索除了前缀之外的每个指令代码类型的指令，将紧接在前的指令与检索到的指令相加，并将结果输出到执行指令 手段。 当在要搜索的多个指令单元中检测到目标指令代码类型的指令时，电路将检测到的指令代码和除目标指令代码类型之外的紧接在前的指令输出作为前缀代码候选。 当在要搜索的指令单元的后端不能检测到目标指令代码类型的指令时，该电路将后端的指令输出为前缀代码候选。 当在指令代码搜索中的头部检测到目标指令代码类型的指令时，电路在头部输出指令代码。

公开(公告)号：US07568084B2

公开(公告)日：2009-07-28

申请号：US10886616

申请日：2004-07-09

申请人： Hiroshi Tanaka ,  Yohei Akita ,  Tetsuro Honmura ,  Fumio Arakawa ,  Takanobu Tsunoda

发明人： Hiroshi Tanaka ,  Yohei Akita ,  Tetsuro Honmura ,  Fumio Arakawa ,  Takanobu Tsunoda

IPC分类号： G06F15/00

CPC分类号： H03K19/17752 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

摘要翻译： 能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。 该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径 切换OSW。 包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持 从多个数据输入节点中的任何一个输入的数据。

公开(公告)号：US07447887B2

公开(公告)日：2008-11-04

申请号：US11482073

申请日：2006-07-07

申请人： Fumio Arakawa

发明人： Fumio Arakawa

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/30185 ,  G06F9/3836

摘要： To guarantee response time while strictly maintaining the priority specified by software, a processor (1) which is a multithread processor having a thread multiplexer (10), and an issue information buffer (ISINF). An instruction code, and issue information (isid) for instructions issued at and after the next operating cycle which is added to the instruction code, are supplied to the thread multiplexer. The issue information is valid from the second and subsequent instruction flows, and is saved temporarily in an issue information buffer. This issue information is for example the position of an operating cycle which can issue a high priority instruction, i.e., information showing a slot. The thread multiplexer issues a low priority instruction at another operating cycle at which a high priority instruction is not issued according to the issue information.

摘要翻译： 为了保证响应时间，同时严格保持由软件指定的优先级，处理器（1）是具有线程多路复用器（10）的多线程处理器和发布信息缓冲器（ISINF）。 对于添加到指令代码中的下一个操作周期和之后发出的指令的指令代码和发出信息（isid）被提供给线程多路复用器。 问题信息从第二个和随后的指令流中有效，并被临时保存在发布信息缓冲区中。 该问题信息例如是可以发出高优先级指令的操作周期的位置，即表示时隙的信息。 线程多路复用器根据问题信息在另一个操作周期发出低优先级指令，在该操作周期不发出高优先级指令。

公开(公告)号：US07222244B2

公开(公告)日：2007-05-22

申请号：US09932099

申请日：2001-08-20

申请人： Takayuki Kawahara ,  Takehiro Shimizu ,  Fumio Arakawa ,  Hiroyuki Mizuno ,  Takao Watanabe ,  Koichiro Ishibashi

发明人： Takayuki Kawahara ,  Takehiro Shimizu ,  Fumio Arakawa ,  Hiroyuki Mizuno ,  Takao Watanabe ,  Koichiro Ishibashi

IPC分类号： G06F1/32

CPC分类号： H03K19/0016 ,  H03K19/1735

摘要： A semiconductor device having a functional circuit block with predictive power controller is provided so as to construct a system LSI manufactured in a practicable number of design steps, which is extensible and in which power is reduced. The functional circuit block includes a prediction circuit and a predictive power shutdown circuit having a power status control circuit. The prediction circuit controls a power status of the functional circuit block by using the power status control circuit, based on input information thereto. When no information is inputted for a predetermined a period of time, the power status control circuit shifts from a power status of the functional circuit block to a low-power status.

摘要翻译： 提供具有预测功率控制器的具有功能电路块的半导体器件，以便构建以可实施的数量的设计步骤制造的系统LSI，其是可扩展的并且功率减小。 功能电路块包括具有电源状态控制电路的预测电路和预测功率关断电路。 预测电路根据其输入信息，通过使用电源状态控制电路来控制功能电路块的电源状态。 当在预定的一段时间内没有输入信息时，电源状态控制电路从功能电路块的电源状态转换为低功率状态。

公开(公告)号：US20070088934A1

公开(公告)日：2007-04-19

申请号：US11482073

申请日：2006-07-07

申请人： Fumio Arakawa

发明人： Fumio Arakawa

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30185 ,  G06F9/3836

摘要： To guarantee response time while strictly maintaining the priority specified by software, a processor (1) which is a multithread processor having a thread multiplexer (10), and an issue information buffer (ISINF). An instruction code, and issue information (isid) for instructions issued at and after the next operating cycle which is added to the instruction code, are supplied to the thread multiplexer. The issue information is valid from the second and subsequent instruction flows, and is saved temporarily in an issue information buffer. This issue information is for example the position of an operating cycle which can issue a high priority instruction, i.e., information showing a slot. The thread multiplexer issues a low priority instruction at another operating cycle at which a high priority instruction is not issued according to the issue information.

摘要翻译： 为了保证响应时间，同时严格保持由软件指定的优先级，处理器（1）是具有线程多路复用器（10）的多线程处理器和发布信息缓冲器（ISINF）。 对于添加到指令代码中的下一个操作周期和之后发出的指令的指令代码和发出信息（isid）被提供给线程多路复用器。 问题信息从第二个和随后的指令流中有效，并被临时保存在发布信息缓冲区中。 该问题信息例如是可以发出高优先级指令的操作周期的位置，即表示时隙的信息。 线程多路复用器根据问题信息在另一个操作周期发出低优先级指令，在该操作周期不发出高优先级指令。

公开(公告)号：US20060004985A1

公开(公告)日：2006-01-05

申请号：US11212736

申请日：2005-08-29

申请人： Fumio Arakawa ,  Tetsuya Yamada

发明人： Fumio Arakawa ,  Tetsuya Yamada

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/3877 ,  G06F9/3887 ,  G06F15/8023 ,  G06F15/8092

摘要： A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining the efficiency of the floating-point length-4 vector inner product execution units is to be implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.

公开(公告)号：US20050268123A1

公开(公告)日：2005-12-01

申请号：US10933292

申请日：2004-09-03

申请人： Fumio Arakawa

发明人： Fumio Arakawa

IPC分类号： G06F1/28 ,  G06F1/30 ,  G06F1/32 ,  G06F15/78 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/171

摘要： A semiconductor device having a plurality of modules is provided which enables each module to perform properly while managing allowable power for an entire chip through power control based on distributed control. A predetermined power consumption value is defined for each module. The predetermined power consumption value refers to power consumption defined taking into account allowable power values for a plurality of modules. Each module takes and regards a difference between the predetermined power consumption value and an actual power consumption value as extra power and notifies other modules of extra power thereof. To avoid a deadlock, each module is designed to be capable of perform data processing below the predetermined power consumption value without using extra power from another module. When notified of extra power by another module, each module can use for data processing electric power that equals to the predetermined power consumption thereof and the extra power notified thereto.

摘要翻译： 提供了具有多个模块的半导体器件，其通过基于分布式控制的功率控制，使得每个模块能够正确地执行整个芯片的允许功率。 为每个模块定义预定的功耗值。 预定功耗值是指考虑到多个模块的可允许功率值而定义的功耗。 每个模块将预定功耗值和实际功耗值之间的差异视为额外功率，并向其他模块通知额外功率。 为了避免死锁，每个模块被设计为能够在不使用来自另一个模块的额外功率的情况下执行低于预定功耗值的数据处理。 当被另一个模块通知额外功率时，每个模块可以使用等于其预定功耗的数据处理电力和通知其的额外功率。

公开(公告)号：US20050015572A1

公开(公告)日：2005-01-20

申请号：US10886616

申请日：2004-07-09

申请人： Hiroshi Tanaka ,  Yohei Akita ,  Tetsuro Honmura ,  Fumio Arakawa ,  Takanobu Tsunoda

发明人： Hiroshi Tanaka ,  Yohei Akita ,  Tetsuro Honmura ,  Fumio Arakawa ,  Takanobu Tsunoda

IPC分类号： H01L21/82 ,  G06F15/80 ,  H03K19/177 ,  G06F15/00

CPC分类号： H03K19/17752 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

摘要翻译： 能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。 该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径 切换OSW。 包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持 从多个数据输入节点中的任何一个输入的数据。

公开(公告)号：US06327605B2

公开(公告)日：2001-12-04

申请号：US09810485

申请日：2001-03-19

申请人： Fumio Arakawa ,  Norio Nakagawa ,  Tetsuya Yamada ,  Yonetaro Totsuka

发明人： Fumio Arakawa ,  Norio Nakagawa ,  Tetsuya Yamada ,  Yonetaro Totsuka

IPC分类号： G06F738

CPC分类号： G06F7/509 ,  G06F7/483 ,  G06F7/5443 ,  G06F7/548 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3885 ,  G06F9/3887

摘要： A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.