公开(公告)号：US07423499B2

公开(公告)日：2008-09-09

申请号：US11546260

申请日：2006-10-12

申请人： Masakazu Adachi ,  Tadayoshi Nakatsuka

发明人： Masakazu Adachi ,  Tadayoshi Nakatsuka

IPC分类号： H01P1/10 ,  H01P1/15

CPC分类号： H01P1/15

摘要： A high-frequency switching apparatus is composed of a transfer circuit unit including a plurality of FETs, and a shunt circuit unit including a plurality of FETs, as well. An electromagnetic wave absorption material element is connected to an end of the shunt circuit unit. To a connection point between the shunt circuit unit and the electromagnetic wave absorption material element, an external voltage terminal for fixing a potential at the point is connected. By this, a high-frequency switching apparatus is obtained which is excellent in isolation characteristics and is hard to break down even when a signal of a high voltage, such as an electrostatic surge, flows into the apparatus.

摘要翻译： 高频开关装置由包括多个FET的转移电路单元和包括多个FET的分流电路单元构成。 电磁波吸收材料元件连接到分流电路单元的一端。 对于分流电路单元和电磁波吸收材料元件之间的连接点，连接用于固定电位的外部电压端子。 由此，获得隔离特性优异的高频开关装置，即使静电浪涌等高电压信号流入装置也难以分解。

公开(公告)号：US07265604B2

公开(公告)日：2007-09-04

申请号：US11285152

申请日：2005-11-23

申请人： Eiji Yasuda ,  Tadayoshi Nakatsuka

发明人： Eiji Yasuda ,  Tadayoshi Nakatsuka

IPC分类号： H03K17/785

CPC分类号： H03K17/693

摘要： A high-frequency switch circuit arrangement. A plurality of stages (for example, two stages) of capacitative elements connected in series (C11 and C12, C21 and C22) are used in a shunt path of a high-frequency component. If a surge voltage is applied, the voltage that each capacitative element should bear decreases in inverse proportion to the number of the connection stages. Consequently, the surge resistance of the capacitative element is improved. The capacitative elements connected in series can be manufactured using the usual manufacturing process of compound semiconductor devices and if the structure of the invention is adopted, a protective diode need not be provided. As the capacity is made common and the device structure is designed, the high-frequency switch circuit arrangement can be further made compact, etc.

摘要翻译： 一种高频开关电路装置。 在高频分量的分流路径中使用串联连接的电容元件（C 11和C 12，C 21和C 22）的多个级（例如两级）。 如果施加浪涌电压，则每个电容元件应承受的电压与连接级的数量成反比。 因此，提高了电容元件的浪涌电阻。 可以使用化合物半导体器件的通常的制造工艺来制造串联连接的电容元件，如果采用本发明的结构，则不需要提供保护二极管。 随着容量的普及和器件结构的设计，高频开关电路的布置可以进一步做到紧凑等。

公开(公告)号：US20090086394A1

公开(公告)日：2009-04-02

申请号：US12237066

申请日：2008-09-24

申请人： Eiji Yasuda ,  Tadayoshi Nakatsuka

发明人： Eiji Yasuda ,  Tadayoshi Nakatsuka

IPC分类号： H02H9/04 ,  H01L27/06

CPC分类号： H02H9/046 ,  H01L27/0266

摘要： In a circuit in which a protected element 42 is connected between an input terminal 61 and an output terminal 62, and a protected element 41 is connected between the input terminal 61 and a reference potential terminal 71, the protected element 41 and a protection circuit 51 are connected in parallel with each other. The protection circuit 51 includes: a field-effect transistor (FET) 11 having a drain connected to the input terminal 61 and a source connected to the reference potential terminal 71; a resistance 31 having one end connected to a gate of the FET 11; a resistance 32 for connecting the other end of the resistance 31 to the source of the FET 11; and a capacitor 21 for connecting the other end of the resistance 31 to the drain of the FET 11.

摘要翻译： 在保护元件42连接在输入端子61和输出端子62之间的电路中，受保护元件41连接在输入端子61和基准电位端子71之间，受保护元件41和保护电路51 彼此并联连接。 保护电路51包括：具有连接到输入端子61的漏极和连接到参考电位端子71的源极的场效应晶体管（FET）11; 电阻31的一端连接到FET11的栅极; 用于将电阻31的另一端连接到FET11的源极的电阻32; 以及用于将电阻31的另一端连接到FET 11的漏极的电容器21。

公开(公告)号：US20070290744A1

公开(公告)日：2007-12-20

申请号：US11806303

申请日：2007-05-31

申请人： Masakazu Adachi ,  Tadayoshi Nakatsuka

发明人： Masakazu Adachi ,  Tadayoshi Nakatsuka

IPC分类号： H03F1/14

CPC分类号： H03F3/24 ,  H01L2924/0002 ,  H03K17/102 ,  H03K17/693 ,  H03K2017/6875 ,  H03K2217/0054 ,  H01L2924/00

摘要： The present invention provides an inexpensive radio frequency switching circuit having desirable radio frequency characteristics over a wide band and desirable endurance against the inflow of a high voltage signal such as an electrostatic surge. Either a negative bias voltage or a positive bias voltage being greater than or equal to 0V and less than or equal to a Schottky forward voltage is used for the control terminals V11 and V12 for controlling FETs 11 to 18 and FETs 21 to 28 so as to turn ON/OFF the path extending from the first input/output terminal P11 to the second input/output terminal P12 and the path extending from the first input/output terminal P11 to the third input/output terminal P13. Thus, it is possible to eliminate the need for DC cut capacitors.

摘要翻译： 本发明提供了一种廉价的射频切换电路，其在宽带上具有期望的射频特性，并且能够抵抗诸如静电浪涌的高电压信号的流入。 对于用于控制FET 11至18和FET 21至28的控制端子V 11和V 12，使用大于或等于0V且小于或等于肖特基正向电压的负偏压或正偏压，因此 用于将从第一输入/输出端子P11延伸到第二输入/输出端子P12的路径和从第一输入/输出端子P11延伸到第三输入/输出端子P13的路径的ON / OFF。 因此，可以消除对直流切断电容器的需要。

公开(公告)号：US20060252394A1

公开(公告)日：2006-11-09

申请号：US11405447

申请日：2006-04-18

申请人： Atsushi Suwa ,  Tadayoshi Nakatsuka

发明人： Atsushi Suwa ,  Tadayoshi Nakatsuka

IPC分类号： H04B1/06

CPC分类号： H04B1/48

摘要： A switching circuit includes: an antenna terminal; a plurality of input/output terminals each for receiving and outputting a signal; and a plurality of basic switching sections each connected between the antenna terminal and an associated one of the input/output terminals. Each of the basic switching sections includes: a through switch formed by FETs connected in series; and a shunt switch. The sources of the FETs forming the through switch and the shunt switch are connected to a first potential fixing terminal through resistors. The resistor connected to the source of the FET at the first stage in the shunt switch is connected to a potential fixing terminal through a diode connected in the forward direction.

摘要翻译： 开关电路包括：天线端子; 多个输入/输出端子，用于接收和输出信号; 以及多个基本切换部，其各自连接在天线端子和相关联的输入/输出端子之间。 每个基本开关部分包括：由串联连接的FET构成的直通开关; 和分流开关。 形成贯通开关的FET和分流开关的源极通过电阻器连接到第一电位固定端子。 在并联开关的第一级连接到FET的源极的电阻器通过沿正向连接的二极管连接到电位固定端子。

公开(公告)号：US07012285B2

公开(公告)日：2006-03-14

申请号：US10416261

申请日：2002-09-12

申请人： Tadayoshi Nakatsuka ,  Toshiharu Tambo ,  Takahiro Kitazawa ,  Akiyoshi Tamura ,  Katsuyoshi Tara

发明人： Tadayoshi Nakatsuka ,  Toshiharu Tambo ,  Takahiro Kitazawa ,  Akiyoshi Tamura ,  Katsuyoshi Tara

IPC分类号： H01L31/072

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0811

摘要： A semiconductor device whose insertion loss is reduced and isolation characteristics are improved in a high frequency band by reducing the capacitance component when an FET is off is provided. FETs (30a, 30b) having a gate electrode with a gate length of not more than 0.8 μm are formed on a semiconductor substrate in which a buffer layer (24) having an impurity concentration of at least 1010 cm−3 and at most 1014 cm−3 is formed on a semi-insulating semiconductor (25) having at least 1014 cm−3 and at most 1016 cm−3 p-type or n-type impurities and an active layer (23) having a p-type or n-type impurity concentration of at least 1015 cm−3 and at most 1017 cm−3 is formed on the buffer layer. N FETs are combined with each other, and when 1≦m≦n−1 (n and m are integers, n>1), a drain terminal of an m-th FET is connected to a source terminal of an (m+1)th FET, resistors (41a, 41b) are connected to the gate electrodes of all of the first to n-th FETs, and all of the other ends of the resistors are coupled to the same electric potential.

摘要翻译： 提供了一种通过在FET断开时减小电容分量来降低插入损耗并且在高频带中提高隔离特性的半导体器件。 具有栅极长度不大于0.8μm的栅电极的FET（30a，30b）形成在半导体衬底上，其中杂质浓度为至少10 <10微米的缓冲层（24） 在半绝缘半导体（25）上形成有至少10×10 -3Ω/ cm 3以上的至少10 SUP> 14 -3 以及至多10×16 / cm 3的p型或n型杂质和活性物质 p型或n型杂质浓度为至少10〜30厘米-3以上且至多10〜17厘米的层（23） 在缓冲层上形成 ^{-3。 N个FET彼此组合，并且当1 <= m <= n-1（n和m是整数，n> 1）时，第m个FET的漏极端子连接到（m +1）个FET，电阻器（41a，41b）连接到所有第一至第N个FET的栅电极，并且电阻器的所有另一端耦合到相同的电位。}

公开(公告)号：US20050270083A1

公开(公告)日：2005-12-08

申请号：US11134351

申请日：2005-05-23

申请人： Tadayoshi Nakatsuka ,  Shigeru Kataoka

发明人： Tadayoshi Nakatsuka ,  Shigeru Kataoka

IPC分类号： H01P1/15 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H03F3/195 ,  H03F3/21 ,  H03F3/217 ,  H03F3/72 ,  H03K17/10 ,  H03K17/62 ,  H03K17/693

CPC分类号： H03F3/195 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/088 ,  H03F3/211 ,  H03F3/72

摘要： A radio frequency switching circuit includes a plurality of input/output terminals for inputting/outputting a radio frequency signal and a plurality of basic switching sections each being provided between adjacent two of the plurality of the input/output terminals. Each of the basic switching sections includes three or more field effect transistors connected in series. Each of two of the field effect transistors connected in series which are located in both ends of the basic switching section, respectively, has a higher threshold voltage than respective threshold voltages of other ones of the field effect transistors.

摘要翻译： 射频切换电路包括多个用于输入/输出射频信号的输入/输出端子和多个基本切换部分，每个基本切换部分设置在多个输入/输出端子的相邻两个之间。 每个基本开关部分包括串联连接的三个或更多个场效应晶体管。 串联连接的位于基本开关部分两端的两个场效应晶体管中的每一个分别具有比其他场效应晶体管的相应阈值电压更高的阈值电压。

公开(公告)号：US5752182A

公开(公告)日：1998-05-12

申请号：US433926

申请日：1995-05-02

申请人： Tadayoshi Nakatsuka ,  Junji Itoh ,  Shinji Yamamoto ,  Mitsuru Nishitsuji

发明人： Tadayoshi Nakatsuka ,  Junji Itoh ,  Shinji Yamamoto ,  Mitsuru Nishitsuji

IPC分类号： H01L23/64 ,  H01L25/16 ,  H03F3/195 ,  H05K1/16 ,  H05K3/40 ,  H04B1/28

CPC分类号： H03F3/195 ,  H01L23/645 ,  H01L23/647 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15159 ,  H01L2924/15162 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/165 ,  H05K3/403

摘要： On a ceramic substrate, spiral-type inductors of a single layer wiring of a metal thin film are provided and respectively connected to a wiring pattern formed on another face of the substrate via through holes. A semiconductor chip is flip-chip mounted on the substrate in a face-down manner. On the face of the semiconductor chip, capacitors composed of a highly dielectric material, resistors formed by an ion implantation method or a thin-film forming method, and FETs are provided, respectively. Interconnection between the substrate and an external circuit board is achieved employing terminals formed at end faces of the substrate. The terminals have a concave shape with respect to the end face of the substrate. Thus, there is no need to use a package, and miniaturization and reduction in cost of a high-performance hybrid IC is achieved.

摘要翻译： 在陶瓷基板上，设置金属薄膜的单层布线的螺旋型电感器，并分别通过通孔与形成在基板的另一面上的布线图案连接。 半导体芯片以面朝下的方式倒装安装在基板上。 在半导体芯片的表面上，分别提供由高介电材料构成的电容器，通过离子注入法形成的电阻或薄膜形成方法以及FET。 使用在基板的端面形成的端子来实现基板与外部电路基板之间的互连。 端子相对于基板的端面具有凹形。 因此，不需要使用封装，并且实现了高性能混合IC的小型化和降低成本。

公开(公告)号：US5461265A

公开(公告)日：1995-10-24

申请号：US54248

申请日：1993-04-30

申请人： Taketo Kunihisa ,  Tadayoshi Nakatsuka

发明人： Taketo Kunihisa ,  Tadayoshi Nakatsuka

IPC分类号： H03G1/00 ,  H03H11/24 ,  H03K17/56

CPC分类号： H03G1/007 ,  H03H11/245

摘要： A variable impedance element suitable for controlling a high-frequency signal is formed of a pair of FETs of identical conduction type, and functions to prevent variations in degree of channel opening of the FETs in response to positive and negative-going changes of the controlled signal voltage, to thereby achieve high linearity of impedance characteristics. Each FET has the drain and gate electrodes mutually coupled by a capacitor, the source electrodes of the FETs are mutually coupled, the gate electrodes are mutually isolated with respect to the high-frequency signal and coupled in common to receive an impedance control voltage, and the variable impedance appears between the drain electrodes.

摘要翻译： 适用于控制高频信号的可变阻抗元件由具有相同导电类型的一对FET形成，并且用于防止响应于受控信号的正负变化而导致的FET的沟道开路程度的变化 电压，从而实现高线性阻抗特性。 每个FET具有由电容器相互耦合的漏极和栅电极，FET的源极电极相互耦合，栅电极相对于高频信号相互隔离并共同耦合以接收阻抗控制电压，以及 漏电极之间出现可变阻抗。

公开(公告)号：US5210504A

公开(公告)日：1993-05-11

申请号：US851900

申请日：1992-03-16

申请人： Hideki Yagita ,  Tadayoshi Nakatsuka ,  Taketo Kunihisa ,  Michiaki Tsuneoka ,  Yukio Sakai ,  Kazuhiro Yahata

发明人： Hideki Yagita ,  Tadayoshi Nakatsuka ,  Taketo Kunihisa ,  Michiaki Tsuneoka ,  Yukio Sakai ,  Kazuhiro Yahata

IPC分类号： H03D7/14 ,  H03F3/45 ,  H03G1/00 ,  H03G3/10 ,  H03G3/30

CPC分类号： H03G1/007

摘要： A semiconductor device for a tuner capable of simultaneously satisfying a low noise factor, low third order distortion characteristics and low power consumption, and a tuner using this semiconductor device for a tuner and capable of reducing the size and eliminating labor during assembly. The semiconductor device is a variable gain amplification circuit comprising a gate grounded circuit using a transistor, and a differential amplification circuit including transistors and constant current sources. Transistors are used as variable resistance devices, and the gain of the gate grounded circuit can be varied by changing the gate voltage of a transistor. The gain of the differential amplification circuit can be varied by changing the gate voltage of another transistor. The overall gain of the circuit can be varied within a necessary range by simultaneously operating these gain controls, and the third order distortion can be improved monotonously with the decrease of the gain.