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公开(公告)号：US5210504A
公开(公告)日：1993-05-11
申请号：US851900
申请日：1992-03-16
申请人： Hideki Yagita , Tadayoshi Nakatsuka , Taketo Kunihisa , Michiaki Tsuneoka , Yukio Sakai , Kazuhiro Yahata
发明人： Hideki Yagita , Tadayoshi Nakatsuka , Taketo Kunihisa , Michiaki Tsuneoka , Yukio Sakai , Kazuhiro Yahata
CPC分类号： H03G1/007
摘要： A semiconductor device for a tuner capable of simultaneously satisfying a low noise factor, low third order distortion characteristics and low power consumption, and a tuner using this semiconductor device for a tuner and capable of reducing the size and eliminating labor during assembly. The semiconductor device is a variable gain amplification circuit comprising a gate grounded circuit using a transistor, and a differential amplification circuit including transistors and constant current sources. Transistors are used as variable resistance devices, and the gain of the gate grounded circuit can be varied by changing the gate voltage of a transistor. The gain of the differential amplification circuit can be varied by changing the gate voltage of another transistor. The overall gain of the circuit can be varied within a necessary range by simultaneously operating these gain controls, and the third order distortion can be improved monotonously with the decrease of the gain.
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公开(公告)号：US5319318A
公开(公告)日：1994-06-07
申请号：US931711
申请日：1992-08-18
摘要： A gain control circuit includes a first FET for serving as an active load, a second FET serving as an amplifier, and a third FET for serving as a current source. The first, second, and third FETs have substantially the same characteristics and are mutually connected in a series. The gain control circuit further includes a fourth FET for serving as a variable active load connected in parallel with the third FET and a capacitor connected between the third and fourth FETs. The fourth FET is also connected to a gain control terminal. The gain of the second FET is controlled by the voltage applied to the gate of the fourth FET through said gain control line.
摘要翻译： 增益控制电路包括用作有源负载的第一FET，用作放大器的第二FET和用作电流源的第三FET。 第一，第二和第三FET具有基本上相同的特性并且串联地相互连接。 增益控制电路还包括用作与第三FET并联连接的可变有源负载的第四FET和连接在第三和第四FET之间的电容器。 第四FET也连接到增益控制端子。 第二FET的增益由通过所述增益控制线施加到第四FET的栅极的电压来控制。
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3.发明申请High-frequency switch circuit, semiconductor device and communication terminal apparatus 审中-公开高频开关电路，半导体装置及通讯终端装置公开(公告)号：US20070085592A1
公开(公告)日：2007-04-19
申请号：US11518167
申请日：2006-09-11
IPC分类号： H03K17/687
CPC分类号： H03K17/6871 , H03K17/063 , H03K17/693 , H04B1/44
摘要： In a high-frequency switch circuit having a booster circuit and a voltage switch circuit for ON/OFF control of the booster circuit, the voltage switch circuit has a means for gradually dropping the gate input voltage and the drain/source input voltage of a series of FETs over a voltage drop time of 10 μsec or more at the time of switching from a boosted voltage to a non-boosted voltage.
摘要翻译： 在具有升压电路和用于升压电路的ON / OFF控制的电压开关电路的高频开关电路中，电压开关电路具有逐渐降低栅极输入电压和串联的漏极/源极输入电压的装置 的FET在从升压电压切换到非升压电压时的电压下降时间为10个以上。
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4.发明授权High-frequency variable impedance circuit having improved linearity of operating characteristics 失效高频可变阻抗电路具有提高的工作特性线性度
公开(公告)号：US5461265A
公开(公告)日：1995-10-24
申请号：US54248
申请日：1993-04-30
CPC分类号： H03G1/007 , H03H11/245
摘要： A variable impedance element suitable for controlling a high-frequency signal is formed of a pair of FETs of identical conduction type, and functions to prevent variations in degree of channel opening of the FETs in response to positive and negative-going changes of the controlled signal voltage, to thereby achieve high linearity of impedance characteristics. Each FET has the drain and gate electrodes mutually coupled by a capacitor, the source electrodes of the FETs are mutually coupled, the gate electrodes are mutually isolated with respect to the high-frequency signal and coupled in common to receive an impedance control voltage, and the variable impedance appears between the drain electrodes.
摘要翻译： 适用于控制高频信号的可变阻抗元件由具有相同导电类型的一对FET形成，并且用于防止响应于受控信号的正负变化而导致的FET的沟道开路程度的变化 电压，从而实现高线性阻抗特性。 每个FET具有由电容器相互耦合的漏极和栅电极，FET的源极电极相互耦合，栅电极相对于高频信号相互隔离并共同耦合以接收阻抗控制电压，以及 漏电极之间出现可变阻抗。
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公开(公告)号：US06756683B2
公开(公告)日：2004-06-29
申请号：US10122514
申请日：2002-04-15
IPC分类号： H01L2348
CPC分类号： H01L23/66 , H01L2224/16 , H01L2224/45144 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/19011 , H01L2924/00
摘要： A semiconductor device includes a silicon substrate with a resistivity being raised by diffusing Au etc. therein, and includes both active elements and passive elements. The active elements are all placed within a semiconductor chip, and the semiconductor chip is flip-chip mounted over the silicon substrate. Such a case where the silicon substrate is heated due to a heating process for forming the active elements can be avoided, and therefore, diffusion of Au etc. from the silicon substrate into the semiconductor device can be avoided.
摘要翻译： 半导体器件包括通过在其中扩散Au等而提高电阻率的硅衬底，并且包括有源元件和无源元件。 有源元件都放置在半导体芯片内，半导体芯片被倒装安装在硅衬底上。 可以避免由于用于形成有源元件的加热处理来加热硅衬底的情况，因此可以避免Au等从硅衬底扩散到半导体器件中。
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公开(公告)号：US6046501A
公开(公告)日：2000-04-04
申请号：US942443
申请日：1997-10-01
申请人： Osamu Ishikawa , Takahiro Yokoyama , Taketo Kunihisa , Masaaki Nishijima , Shinji Yamamoto , Junji Itoh , Toshio Fujiwara , Kaoru Muramatsu
发明人： Osamu Ishikawa , Takahiro Yokoyama , Taketo Kunihisa , Masaaki Nishijima , Shinji Yamamoto , Junji Itoh , Toshio Fujiwara , Kaoru Muramatsu
IPC分类号： H01L23/31 , H01L23/433 , H01L23/495 , H01L23/66 , H05K1/02 , H05K3/34 , H01L23/04 , H01L23/34
CPC分类号： H05K3/341 , H01L23/3107 , H01L23/4334 , H01L23/49503 , H01L23/66 , H01L2224/27013 , H01L2924/13091 , H01L2924/15153 , H01L2924/15165 , H01L2924/3011 , H05K1/0243 , H05K2201/10689 , H05K2201/10931 , H05K2201/10969 , Y02P70/613
摘要： An RF-driven semiconductor chip is die-bonded to the top face of a metal plate. The semiconductor chip and the metal plate are molded together with outer leads in a plastic package in the form of a rectangular parallelepiped. The metal plate is exposed at the back face of the plastic package. The metal plate is not protruding from the front and rear side faces of the plastic package. The front and rear side faces of the metal plate are flush with the front and rear side faces of the plastic package and partially exposed at the front and rear side faces of the plastic package. The front and rear portions of the plastic package are centrally formed with respective cutaway portions each in the form of a rectangular parallelepiped. The top face of the metal plate is exposed in the cutaway portions formed centrally in the front and rear portions of the plastic package to form solder portions.
摘要翻译： RF驱动的半导体芯片与金属板的顶面芯片接合。 半导体芯片和金属板与塑料封装中的外引线一起模塑成长方体形状。 金属板在塑料包装的背面露出。 金属板不会从塑料封装的前后侧面突出。 金属板的前侧面和后侧面与塑料包装件的前侧面和后侧面齐平，并部分地暴露在塑料包装件的前侧和后侧面。 塑料包装件的前部和后部中心地形成有各自的切割部分，每个切口部分呈矩形平行六面体形式。 金属板的顶面露出在塑料封装的前后部中央形成的切口部，形成焊料部。
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公开(公告)号：US06313699B1
公开(公告)日：2001-11-06
申请号：US09593123
申请日：2000-06-13
IPC分类号： H03F114
CPC分类号： H03F3/68 , H03F3/602 , H03F3/72 , H03F2200/294 , H03F2200/372 , H03F2203/7215 , H03F2203/7221 , H03F2203/7231 , H03F2203/7233 , H03F2203/7236
摘要： A power amplifier including: a first amplifier PA2 having an input terminal and an output terminal; a passive circuit PC3 having an input terminal and an output terminal; and a first switch SW2 having a single-pole terminal and two multi-throw terminals, one of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the first amplifier PA2 and the other of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the passive circuit PC3. This makes it possible to provide a power amplifier and a communication unit which can be operated with different frequencies, output powers or modulation types.
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公开(公告)号：US07692470B2
公开(公告)日：2010-04-06
申请号：US12181729
申请日：2008-07-29
IPC分类号： H03L5/00
CPC分类号： H03K19/0013 , H03K19/018507
摘要： A level conversion circuit according to the present invention comprises: a first transistor having a gate thereof grounded, for inputting the input voltage to a source thereof and outputting an output voltage from a drain thereof; a second transistor having a drain thereof to which a power supply voltage is applied, for inputting the output voltage outputted from the drain of the first transistor to a gate thereof and outputting, from a source thereof, the output voltage determined by the power supply voltage; a level shift circuit for inputting the output voltage outputted from the source of the second transistor to an input end thereof and outputting, from an output end thereof, a voltage whose level is shifted by a predetermined amount; and a resistance inserted between the output end of the level shift circuit and a ground. Thus, it becomes possible to reduce a current Ii flowing to the gate of the first transistor to a level close to zero.
摘要翻译： 根据本发明的电平转换电路包括：第一晶体管，其栅极接地，用于将输入电压输入到其源极，并从其漏极输出输出电压; 第二晶体管，其漏极施加有电源电压，用于将从第一晶体管的漏极输出的输出电压输入到其栅极，并从其源极输出由电源电压确定的输出电压 ; 电平移位电路，用于将从第二晶体管的源极输出的输出电压输入到其输入端，并从其输出端输出电平偏移预定量的电压; 以及插入在电平移位电路的输出端和地之间的电阻。 因此，可以将流过第一晶体管的栅极的电流I i减小到接近零的水平。
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公开(公告)号：US20090033402A1
公开(公告)日：2009-02-05
申请号：US12181729
申请日：2008-07-29
IPC分类号： H03L5/00
CPC分类号： H03K19/0013 , H03K19/018507
摘要： A level conversion circuit according to the present invention comprises: a first transistor having a gate thereof grounded, for inputting the input voltage to a source thereof and outputting an output voltage from a drain thereof; a second transistor having a drain thereof to which a power supply voltage is applied, for inputting the output voltage outputted from the drain of the first transistor to a gate thereof and outputting, from a source thereof, the output voltage determined by the power supply voltage; a level shift circuit for inputting the output voltage outputted from the source of the second transistor to an input end thereof and outputting, from an output end thereof, a voltage whose level is shifted by a predetermined amount; and a resistance inserted between the output end of the level shift circuit and a ground. Thus, it becomes possible to reduce a current Ii flowing to the gate of the first transistor to a level close to zero.
摘要翻译： 根据本发明的电平转换电路包括：第一晶体管，其栅极接地，用于将输入电压输入到其源极，并从其漏极输出输出电压; 第二晶体管，其漏极施加有电源电压，用于将从第一晶体管的漏极输出的输出电压输入到其栅极，并从其源极输出由电源电压确定的输出电压 ; 电平移位电路，用于将从第二晶体管的源极输出的输出电压输入到其输入端，并从其输出端输出电平偏移预定量的电压; 以及插入在电平移位电路的输出端和地之间的电阻。 因此，可以将流过第一晶体管的栅极的电流I i减小到接近零的水平。
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公开(公告)号：US5982236A
公开(公告)日：1999-11-09
申请号：US009241
申请日：1998-01-20
申请人： Osamu Ishikawa , Takahiro Yokoyama , Taketo Kunihisa , Junji Ito , Masaaki Nishijima , Shinji Yamamoto
发明人： Osamu Ishikawa , Takahiro Yokoyama , Taketo Kunihisa , Junji Ito , Masaaki Nishijima , Shinji Yamamoto
CPC分类号： H03F3/601 , H03F1/0261
摘要： A high-frequency power amplifier comprises a transistor for high-frequency power which operates and whose current-voltage characteristics greatly change when positive voltage is supplied on its input terminal, an input bias circuit, an output bias circuit, an input impedance matching circuit, an output impedance matching circuit, and a positive voltage generation circuit. The positive voltage generation circuit comprises a detection circuit which detects part of the high-frequency power which is entered to or outputted from the transistor for high-frequency power, a rectification circuit which rectifies the part of the high-frequency power outputted from the detection circuit and outputs pulsating positive voltage, and a smoothing circuit which smoothes the pulsating positive voltage outputted from the rectification circuit and outputs positive voltage. The positive voltage generation circuit outputs positive voltage which increases or decreases in accordance with an increase or decrease in the detected part of the high-frequency power to the input terminal of the input bias circuit, without intervention of a direct-current power supply.
摘要翻译： 高频功率放大器包括用于高频功率的晶体管，其工作时的电流电压特性在其输入端子上提供正电压，输入偏置电路，输出偏置电路，输入阻抗匹配电路， 输出阻抗匹配电路和正电压发生电路。 正电压发生电路包括：检测电路，其检测输入到高频电源的晶体管或从高频电源的晶体管输出的高频电力的一部分;整流电路，其对检测出的部分高频电力进行整流; 电路和输出脉动正电压，以及平滑电路，其使从整流电路输出的脉动正电压平滑并输出正电压。 正电压发生电路根据高频电源的检测部分对输入偏置电路的输入端子的增加或减少而输出正电压，而不需要直流电源的干预。
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