公开(公告)号：US20060114051A1

公开(公告)日：2006-06-01

申请号：US11285152

申请日：2005-11-23

申请人： Eiji Yasuda ,  Tadayoshi Nakatsuka

发明人： Eiji Yasuda ,  Tadayoshi Nakatsuka

IPC分类号： H03K17/687

CPC分类号： H03K17/693

摘要： A high-frequency switch circuit arrangement. A plurality of stages (for example, two stages) of capacitative elements connected in series (C11 and C12, C21 and C22) are used in a shunt path of a high-frequency component. If a surge voltage is applied, the voltage that each capacitative element should bear decreases in inverse proportion to the number of the connection stages. Consequently, the surge resistance of the capacitative element is improved. The capacitative elements connected in series can be manufactured using the usual manufacturing process of compound semiconductor devices and if the structure of the invention is adopted, a protective diode need not be provided. As the capacity is made common and the device structure is designed, the high-frequency switch circuit arrangement can be further made compact, etc.

摘要翻译： 一种高频开关电路装置。 在高频分量的分流路径中使用串联连接的电容元件（C 11和C 12，C 21和C 22）的多个级（例如两级）。 如果施加浪涌电压，则每个电容元件应承受的电压与连接级的数量成反比。 因此，提高了电容元件的浪涌电阻。 可以使用化合物半导体器件的通常的制造工艺来制造串联连接的电容元件，如果采用本发明的结构，则不需要提供保护二极管。 随着容量的普及和器件结构的设计，高频开关电路的布置可以进一步做到紧凑等。

公开(公告)号：US07541860B2

公开(公告)日：2009-06-02

申请号：US12043310

申请日：2008-03-06

申请人： Eiji Yasuda ,  Tadayoshi Nakatsuka

发明人： Eiji Yasuda ,  Tadayoshi Nakatsuka

IPC分类号： G05F3/00

CPC分类号： H03K19/0185

摘要： When a low level voltage is inputted to an input terminal IN, a transistor EF1 enters a blocked state, a first switch circuit SW1 enters a conduction state, and a second switch circuit SW2 enters the blocked state. Accordingly, a boosted voltage outputted from a voltage booster circuit CP is applied to a load R. When a high level voltage is inputted to the input terminal IN, the transistor EF1 enters the conduction state, the first switch circuit SW1 enters the blocked state, and the second switch circuit SW2 enters the conduction state. Accordingly, a voltage equivalent to that at the external power supply terminal VDD is applied to the load R. Therefore, although a current constantly flows through the transistor EF1 when the boosted voltage is not required, such situation does not affect a current supplied from the voltage booster circuit CP.

摘要翻译： 当低电平电压输入到输入端子IN时，晶体管EF1进入阻塞状态，第一开关电路SW1进入导通状态，第二开关电路SW2进入阻塞状态。 因此，从升压电路CP输出的升压电压被施加到负载R.当向输入端子IN输入高电平电压时，晶体管EF1进入导通状态，第一开关电路SW1进入阻塞状态， 第二开关电路SW2进入导通状态。 因此，与外部电源端子VDD相当的电压被施加到负载R。因此，虽然当不需要升压电压时电流恒定地流过晶体管EF1，但这种情况不影响从 升压电路CP。

公开(公告)号：US07337547B2

公开(公告)日：2008-03-04

申请号：US11169314

申请日：2005-06-29

申请人： Eiji Yasuda ,  Kenichi Hidaka ,  Yasuyuki Masumoto ,  Tadayoshi Nakatsuka ,  Atsushi Watanabe ,  Katsushi Tara

发明人： Eiji Yasuda ,  Kenichi Hidaka ,  Yasuyuki Masumoto ,  Tadayoshi Nakatsuka ,  Atsushi Watanabe ,  Katsushi Tara

IPC分类号： H01P1/10 ,  H01P5/12

CPC分类号： H03K17/693

摘要： A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

摘要翻译： 可以使用多个由肖特基结构成的二极管制成的多个控制电压输入端子的电压中选择高电压的二极管逻辑电路一体形成在复合半导体基板上，在该复合半导体基板上，用于切换和用于固定隔离的MESFET级具有 已经形成。 此外，用于切换的MESFET级由控制电压输入端子的数量的电压控制，用于固定隔离的MESFET级由二极管逻辑电路输出的或电压控制。

公开(公告)号：US07265604B2

公开(公告)日：2007-09-04

申请号：US11285152

申请日：2005-11-23

申请人： Eiji Yasuda ,  Tadayoshi Nakatsuka

发明人： Eiji Yasuda ,  Tadayoshi Nakatsuka

IPC分类号： H03K17/785

CPC分类号： H03K17/693

摘要： A high-frequency switch circuit arrangement. A plurality of stages (for example, two stages) of capacitative elements connected in series (C11 and C12, C21 and C22) are used in a shunt path of a high-frequency component. If a surge voltage is applied, the voltage that each capacitative element should bear decreases in inverse proportion to the number of the connection stages. Consequently, the surge resistance of the capacitative element is improved. The capacitative elements connected in series can be manufactured using the usual manufacturing process of compound semiconductor devices and if the structure of the invention is adopted, a protective diode need not be provided. As the capacity is made common and the device structure is designed, the high-frequency switch circuit arrangement can be further made compact, etc.

摘要翻译： 一种高频开关电路装置。 在高频分量的分流路径中使用串联连接的电容元件（C 11和C 12，C 21和C 22）的多个级（例如两级）。 如果施加浪涌电压，则每个电容元件应承受的电压与连接级的数量成反比。 因此，提高了电容元件的浪涌电阻。 可以使用化合物半导体器件的通常的制造工艺来制造串联连接的电容元件，如果采用本发明的结构，则不需要提供保护二极管。 随着容量的普及和器件结构的设计，高频开关电路的布置可以进一步做到紧凑等。

公开(公告)号：US20070085592A1

公开(公告)日：2007-04-19

申请号：US11518167

申请日：2006-09-11

申请人： Eiji Yasuda ,  Tadayoshi Nakatsuka ,  Toshihiro Shougaki ,  Kenichi Hidaka ,  Taketo Kunihisa

发明人： Eiji Yasuda ,  Tadayoshi Nakatsuka ,  Toshihiro Shougaki ,  Kenichi Hidaka ,  Taketo Kunihisa

IPC分类号： H03K17/687

CPC分类号： H03K17/6871 ,  H03K17/063 ,  H03K17/693 ,  H04B1/44

摘要： In a high-frequency switch circuit having a booster circuit and a voltage switch circuit for ON/OFF control of the booster circuit, the voltage switch circuit has a means for gradually dropping the gate input voltage and the drain/source input voltage of a series of FETs over a voltage drop time of 10 μsec or more at the time of switching from a boosted voltage to a non-boosted voltage.

摘要翻译： 在具有升压电路和用于升压电路的ON / OFF控制的电压开关电路的高频开关电路中，电压开关电路具有逐渐降低栅极输入电压和串联的漏极/源极输入电压的装置 的FET在从升压电压切换到非升压电压时的电压下降时间为10个以上。

公开(公告)号：US20090086394A1

公开(公告)日：2009-04-02

申请号：US12237066

申请日：2008-09-24

申请人： Eiji Yasuda ,  Tadayoshi Nakatsuka

发明人： Eiji Yasuda ,  Tadayoshi Nakatsuka

IPC分类号： H02H9/04 ,  H01L27/06

CPC分类号： H02H9/046 ,  H01L27/0266

摘要： In a circuit in which a protected element 42 is connected between an input terminal 61 and an output terminal 62, and a protected element 41 is connected between the input terminal 61 and a reference potential terminal 71, the protected element 41 and a protection circuit 51 are connected in parallel with each other. The protection circuit 51 includes: a field-effect transistor (FET) 11 having a drain connected to the input terminal 61 and a source connected to the reference potential terminal 71; a resistance 31 having one end connected to a gate of the FET 11; a resistance 32 for connecting the other end of the resistance 31 to the source of the FET 11; and a capacitor 21 for connecting the other end of the resistance 31 to the drain of the FET 11.

摘要翻译： 在保护元件42连接在输入端子61和输出端子62之间的电路中，受保护元件41连接在输入端子61和基准电位端子71之间，受保护元件41和保护电路51 彼此并联连接。 保护电路51包括：具有连接到输入端子61的漏极和连接到参考电位端子71的源极的场效应晶体管（FET）11; 电阻31的一端连接到FET11的栅极; 用于将电阻31的另一端连接到FET11的源极的电阻32; 以及用于将电阻31的另一端连接到FET 11的漏极的电容器21。

公开(公告)号：US20080218240A1

公开(公告)日：2008-09-11

申请号：US12043310

申请日：2008-03-06

申请人： Eiji Yasuda ,  Tadayoshi Nakatsuka

发明人： Eiji Yasuda ,  Tadayoshi Nakatsuka

IPC分类号： H03K19/0185

CPC分类号： H03K19/0185

摘要： When a low level voltage is inputted to an input terminal IN, a transistor EF1 enters a blocked state, a first switch circuit SW1 enters a conduction state, and a second switch circuit SW2 enters the blocked state. Accordingly, a boosted voltage outputted from a voltage booster circuit CP is applied to a load R. When a high level voltage is inputted to the input terminal IN, the transistor EF1 enters the conduction state, the first switch circuit SW1 enters the blocked state, and the second switch circuit SW2 enters the conduction state. Accordingly, a voltage equivalent to that at the external power supply terminal VDD is applied to the load R. Therefore, although a current constantly flows through the transistor EF1 when the boosted voltage is not required, such situation does not affect a current supplied from the voltage booster circuit CP.

摘要翻译： 当低电平电压输入到输入端子IN时，晶体管EF1进入阻塞状态，第一开关电路SW 1进入导通状态，第二开关电路SW 2进入阻塞状态。 因此，从升压电路CP输出的升压电压被施加到负载R.当高电平电压输入到输入端子IN时，晶体管EF1进入导通状态，第一开关电路SW 1进入阻塞状态 状态，第二开关电路SW 2进入导通状态。 因此，与外部电源端子VDD相当的电压被施加到负载R。因此，虽然当不需要升压电压时电流恒定地流过晶体管EF 1，但这种情况不会影响从 升压电路CP。

公开(公告)号：US20060001473A1

公开(公告)日：2006-01-05

申请号：US11169314

申请日：2005-06-29

申请人： Eiji Yasuda ,  Kenichi Hidaka ,  Yasuyuki Masumoto ,  Tadayoshi Nakatsuka ,  Atsushi Watanabe ,  Katsushi Tara

发明人： Eiji Yasuda ,  Kenichi Hidaka ,  Yasuyuki Masumoto ,  Tadayoshi Nakatsuka ,  Atsushi Watanabe ,  Katsushi Tara

IPC分类号： H03K17/62

CPC分类号： H03K17/693

摘要： A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

摘要翻译： 可以使用多个由肖特基结构成的二极管制成的多个控制电压输入端子的电压中选择高电压的二极管逻辑电路一体形成在复合半导体基板上，在该复合半导体基板上，用于切换和用于固定隔离的MESFET级具有 已经形成。 此外，用于切换的MESFET级由控制电压输入端子的数量的电压控制，用于固定隔离的MESFET级由二极管逻辑电路输出的或电压控制。

公开(公告)号：US07492238B2

公开(公告)日：2009-02-17

申请号：US11591462

申请日：2006-11-02

申请人： Tadayoshi Nakatsuka ,  Atsushi Suwa ,  Motoo Nakagawa ,  Masakazu Adachi

发明人： Tadayoshi Nakatsuka ,  Atsushi Suwa ,  Motoo Nakagawa ,  Masakazu Adachi

IPC分类号： H01P1/10 ,  H01P1/15 ,  H03H11/34

CPC分类号： H01P1/15 ,  H03K17/002 ,  H03K17/063 ,  H03K17/102 ,  H03K17/693

摘要： A common terminal 500 is connected to drains of FETs 101 and 102 via a capacitor 400. FETs 111 to 114 are serially connected, and inserted between a source of the FET 101 and a terminal 501 via a capacitor 401. Similarly, each of: FETs 121 to 124; FETs 131 to 133; FETs 141 to 143; FETs 151 to 153; and FETs 161 to 163 is inserted between the source of the FET 101 or an FET 102 and a corresponding one of terminals 502 to 506. This configuration allows a stray capacitance value of a transmission/reception path to be reduced at the time of transmission/reception, thereby obtaining a favorable radio-frequency characteristic.

摘要翻译： 公共端子500经由电容器400连接到FET 101和102的漏极.FET 111至114串联连接，并且经由电容器401插入FET 101的源极和端子501之间。类似地，每个FET 121至124; FET 131〜133; FET 141〜143; FET 151〜153; 并且FET161〜163插入在FET101的源极或FET102与端子502〜506中的对应的一个之间。这种结构允许发送/接收路径的杂散电容值减小， 接收，从而获得有利的射频特性。

公开(公告)号：US07286001B2

公开(公告)日：2007-10-23

申请号：US11402849

申请日：2006-04-13

申请人： Tadayoshi Nakatsuka ,  Katsushi Tara ,  Shinji Fukumoto

发明人： Tadayoshi Nakatsuka ,  Katsushi Tara ,  Shinji Fukumoto

IPC分类号： H03L5/00

CPC分类号： H03K17/102 ,  H03K17/6871 ,  H03K17/693 ,  H03K2217/0036

摘要： The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.

摘要翻译： 多个电阻元件的第一端子连接到串联连接的多个FET的中间连接点，并且具有与施加到多个FET的栅极端子的电压相反的相位的电压为 施加到多个电阻元件的第二端子。 利用这种配置，可以防止串联连接的多个FET的中间连接点处的电位降低。 结果，可以提高可以处理的功率。 此外，由于能够防止串联连接的多个FET的中间连接点的电位降低，所以由于多个FET的中间连接点的电位降低，失真特性和隔离特性的劣化 串联连接的场效应晶体管可以获得优异的高频特性。