公开(公告)号：US20080237695A1

公开(公告)日：2008-10-02

申请号：US11860956

申请日：2007-09-25

申请人： Tomoaki SHINO ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoaki SHINO ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C11/404 ,  G11C11/4074 ,  G11C14/0018 ,  G11C2211/4016 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42344 ,  H01L29/785 ,  H01L29/78648

摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

摘要翻译： 本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态 通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态 通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

公开(公告)号：US20060118873A1

公开(公告)日：2006-06-08

申请号：US11331316

申请日：2006-01-13

申请人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

发明人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

IPC分类号： H01L27/12

CPC分类号： H01L21/823412 ,  H01L21/76264 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7841

摘要： A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

摘要翻译： 半导体器件包括具有第一至第四区域的衬底，在第一区域中的衬底上形成的第一绝缘膜，形成在第二区域中的衬底上并具有高于第一区域的上表面的上表面的第一外延层 绝缘膜，形成在所述第一绝缘膜上的第一半导体层，其具有相对于所述第一外延层设置的空间，并且具有设置在与所述第一外延层的上表面基本相同的高度的上表面;以及元件隔离绝缘膜 膜形成在该空间中，并且具有设置在与第一外延层的上表面和第一半导体层的上表面大致相同高度的上表面。

公开(公告)号：US07032066B2

公开(公告)日：2006-04-18

申请号：US09956346

申请日：2001-09-20

申请人： Takeo Miki ,  Mikio Asakura ,  Takeshi Hamamoto

发明人： Takeo Miki ,  Mikio Asakura ,  Takeshi Hamamoto

IPC分类号： G11C7/10

CPC分类号： G11C5/06 ,  G11C7/10 ,  G11C7/1066 ,  G11C11/4093

摘要： In a semiconductor memory unit to which a plurality of different functions can be imparted by merely changing a portion of its production process, the improvement comprises: a plurality of data buses which include first data buses for use only in one of the functions and the remaining data buses for use in the one and the remainder of the functions; wherein when the semiconductor memory unit performs the remainder of the functions, the first data buses are utilized for the semiconductor memory unit.

公开(公告)号：US07030437B2

公开(公告)日：2006-04-18

申请号：US10443000

申请日：2003-05-22

申请人： Satoshi Yodogawa ,  Satoshi Kawasaki ,  Takeshi Hamamoto

发明人： Satoshi Yodogawa ,  Satoshi Kawasaki ,  Takeshi Hamamoto

IPC分类号： H01L27/108

CPC分类号： H01L27/10873 ,  G11C7/065 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes two sense amplifiers provided on a semiconductor substrate. Each of two sense amplifiers is formed of a pair of transistors. Two transistors are separated from each other by an element-isolating insulating portion provided on the semiconductor substrate. Therefore unlike the conventional, two transistors do not share the source region with each other, resulting in a semiconductor device with an improved sensitivity of a sense amplifier.

摘要翻译： 半导体器件包括设置在半导体衬底上的两个读出放大器。 两个读出放大器中的每一个由一对晶体管构成。 两个晶体管通过设置在半导体衬底上的元件隔离绝缘部分彼此分离。 因此，与传统的不同，两个晶体管彼此不共享源极区域，导致具有改善的读出放大器的灵敏度的半导体器件。

公开(公告)号：US06570174B1

公开(公告)日：2003-05-27

申请号：US09458625

申请日：1999-12-10

申请人： Keiichiro Tounai ,  Takeshi Hamamoto

发明人： Keiichiro Tounai ,  Takeshi Hamamoto

IPC分类号： G01N2186

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： An optical proximity effect correcting method in a semiconductor manufacturing process includes adding, detecting, judging, and deleting. The adding includes adding a first correcting region around a portion of a first design pattern. The portion faces a second design pattern. A first corrected design pattern includes the first correcting region and the first design pattern. The detecting includes detecting a space between the first corrected design pattern and the second design pattern. The judging includes judging whether the space is smaller than or equal to a predetermined value. The deleting includes deleting at least a portion of the first correcting region such that the space is larger than the predetermined value, when the space is smaller than or equal to the predetermined value.

摘要翻译： 半导体制造过程中的光学邻近效应校正方法包括添加，检测，判断和删除。 所述添加包括在第一设计图案的一部分周围添加第一校正区域。 该部分面向第二设计图案。 第一校正设计图案包括第一校正区域和第一设计图案。 检测包括检测第一校正设计图案和第二设计图案之间的空间。 该判断包括判断空间是否小于或等于预定值。 删除包括当空间小于或等于预定值时，删除第一校正区域的至少一部分，使得空间大于预定值。

公开(公告)号：US06567324B2

公开(公告)日：2003-05-20

申请号：US10119782

申请日：2002-04-11

申请人： Tsukasa Ooishi ,  Takeshi Hamamoto

发明人： Tsukasa Ooishi ,  Takeshi Hamamoto

IPC分类号： G11C700

CPC分类号： G11C29/808

摘要： A setting circuit provided at a central part of a chip to set a replacement address includes seven redundancy determining units, each of which includes a program set. Each of four banks are divided into half to provide the total of eight regions. Eight control buses are provided transmitting data corresponding to the eight regions respectively. A bus determining unit selects a corresponding control bus in accordance with the contents of the program set and outputs replacement information. Therefore, each of the seven program sets can be used for replacement in any of the eight regions.

公开(公告)号：US06489819B1

公开(公告)日：2002-12-03

申请号：US09179411

申请日：1998-10-27

申请人： Takashi Kono ,  Takeshi Hamamoto ,  Yasuhiro Konishi

发明人： Takashi Kono ,  Takeshi Hamamoto ,  Yasuhiro Konishi

IPC分类号： G11C700

CPC分类号： G11C29/14

摘要： Pulses are generated using an edge of a clock signal applied from a low speed tester as a trigger, and internal clock signals are generated utilizing the pulses. Internal circuitry is operated in synchronization with the internal clock signals. Thus a synchronous semiconductor device operating at high speed can be tested using a low speed tester.

摘要翻译： 使用从低速测试仪施加的时钟信号的边沿作为触发产生脉冲，并且使用脉冲产生内部时钟信号。 内部电路与内部时钟信号同步工作。 因此，可以使用低速测试仪来测试以高速操作的同步半导体器件。

公开(公告)号：US5987619A

公开(公告)日：1999-11-16

申请号：US947372

申请日：1997-10-08

申请人： Takeshi Hamamoto ,  Masaki Tsukude

发明人： Takeshi Hamamoto ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G06F1/10 ,  G11C11/409 ,  G06F1/04

CPC分类号： G06F1/10

摘要： An input signal phase compensation circuit having a monitor mode and a normal operation mode includes a mode switching circuit, a logic gate receiving an internal data signal, a delay circuit connected to the logic gate, and a phase comparator comparing, in the monitor mode, phases of a signal output from the delay circuit and a clock signal, and determining time for delaying an internal clock signal in a variable delay circuit so as to match phases of the both signals. In the normal operation mode, the time is fixed, and data is obtained at phase compensated timing.

摘要翻译： 具有监视模式和正常操作模式的输入信号相位补偿电路包括模式切换电路，接收内部数据信号的逻辑门，连接到逻辑门的延迟电路，以及在监视器模式下， 从延迟电路输出的信号的相位和时钟信号，以及确定用于延迟可变延迟电路中的内部时钟信号的时间，以便匹配两个信号的相位。 在正常工作模式下，时间是固定的，并且在相位补偿定时获得数据。

公开(公告)号：US5838335A

公开(公告)日：1998-11-17

申请号：US844633

申请日：1997-04-21

申请人： Takeshi Hamamoto

发明人： Takeshi Hamamoto

IPC分类号： H01L21/822 ,  G06F17/50 ,  G06T1/60 ,  H01L21/82 ,  H01L27/04

CPC分类号： G06T1/60

摘要： A graphic data processing device is proposed that enables high-speed graphic processing for repeated graphic in semiconductor layout data. A plurality of sets of systematic array graphic data are inputted in an input device, the inputted systematic array graphic data are checked in an array information analyzer to confirm that the grid widths of the array grids of the different data are equal, and data are converted at an array graphic converter to systematic array graphic data sharing common array grid information. The data can then undergo graphic processing at a graphic processor in the form of systematic array graphic data without further alteration.

摘要翻译： 提出了一种能够对半导体布局数据中的重复图形进行高速图形处理的图形数据处理装置。 在输入装置中输入多组系统阵列图形数据，在阵列信息分析器中检查输入的系统阵列图形数据，以确认不同数据的阵列网格的网格宽度相等，数据被转换 在阵列图形转换器到系统阵列图形数据共享公共阵列网格信息。 然后，数据可以以图形处理器的形式以系统阵列图形数据的形式进行图形处理，而无需进一步的改变。

公开(公告)号：US5736760A

公开(公告)日：1998-04-07

申请号：US632321

申请日：1996-04-15

申请人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

发明人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10829

摘要： A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.