公开(公告)号：US07095081B2

公开(公告)日：2006-08-22

申请号：US11331316

申请日：2006-01-13

申请人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

发明人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00

CPC分类号： H01L21/823412 ,  H01L21/76264 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7841

摘要： A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

摘要翻译： 半导体器件包括具有第一至第四区域的衬底，在第一区域中的衬底上形成的第一绝缘膜，形成在第二区域中的衬底上并具有高于第一区域的上表面的上表面的第一外延层 绝缘膜，形成在所述第一绝缘膜上的第一半导体层，其具有相对于所述第一外延层设置的空间，并且具有设置在与所述第一外延层的上表面基本相同的高度的上表面;以及元件隔离绝缘膜 膜形成在该空间中，并且具有设置在与第一外延层的上表面和第一半导体层的上表面大致相同高度的上表面。

公开(公告)号：US20050045951A1

公开(公告)日：2005-03-03

申请号：US10699676

申请日：2003-11-04

申请人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

发明人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/823412 ,  H01L21/76264 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7841

摘要： A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

摘要翻译： 半导体器件包括具有第一至第四区域的衬底，在第一区域中的衬底上形成的第一绝缘膜，形成在第二区域中的衬底上并具有高于第一区域的上表面的上表面的第一外延层 绝缘膜，形成在所述第一绝缘膜上的第一半导体层，其具有相对于所述第一外延层设置的空间，并且具有设置在与所述第一外延层的上表面基本相同的高度的上表面;以及元件隔离绝缘膜 膜形成在该空间中，并且具有设置在与第一外延层的上表面和第一半导体层的上表面大致相同高度的上表面。

公开(公告)号：US07323748B2

公开(公告)日：2008-01-29

申请号：US11455700

申请日：2006-06-20

申请人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

发明人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00

CPC分类号： H01L21/823412 ,  H01L21/76264 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7841

摘要： A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, and a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer, having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and having a tapered surface faced to a side surface of the first epitaxial layer.

摘要翻译： 半导体器件包括具有第一和第二区域的衬底，在第一区域中的衬底上形成的第一绝缘膜，形成在第二区域中的衬底上并具有高于第一区域的上表面的上表面的第一外延层 绝缘膜和形成在第一绝缘膜上的第一半导体层，其具有相对于第一外延层设置的空间，其上表面设置在与第一外延层的上表面大致相同的高度，并且具有锥形表面 面对第一外延层的侧表面。

公开(公告)号：US20060244065A1

公开(公告)日：2006-11-02

申请号：US11455700

申请日：2006-06-20

申请人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

发明人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

IPC分类号： H01L27/12

CPC分类号： H01L21/823412 ,  H01L21/76264 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7841

摘要： A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, and a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer, having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and having a tapered surface faced to a side surface of the first epitaxial layer.

摘要翻译： 半导体器件包括具有第一和第二区域的衬底，在第一区域中的衬底上形成的第一绝缘膜，形成在第二区域中的衬底上并具有高于第一区域的上表面的上表面的第一外延层 绝缘膜和形成在第一绝缘膜上的第一半导体层，其具有相对于第一外延层设置的空间，其上表面设置在与第一外延层的上表面大致相同的高度，并且具有锥形表面 面对第一外延层的侧表面。

公开(公告)号：US07049661B2

公开(公告)日：2006-05-23

申请号：US10699676

申请日：2003-11-04

申请人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

发明人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00

CPC分类号： H01L21/823412 ,  H01L21/76264 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7841

摘要： A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

摘要翻译： 半导体器件包括具有第一至第四区域的衬底，在第一区域中的衬底上形成的第一绝缘膜，形成在第二区域中的衬底上并具有高于第一区域的上表面的上表面的第一外延层 绝缘膜，形成在所述第一绝缘膜上的第一半导体层，其具有相对于所述第一外延层设置的空间，并且具有设置在与所述第一外延层的上表面基本相同的高度的上表面;以及元件隔离绝缘膜 膜形成在该空间中，并且具有设置在与第一外延层的上表面和第一半导体层的上表面大致相同高度的上表面。

公开(公告)号：US20060118873A1

公开(公告)日：2006-06-08

申请号：US11331316

申请日：2006-01-13

申请人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

发明人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

IPC分类号： H01L27/12

CPC分类号： H01L21/823412 ,  H01L21/76264 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7841

摘要： A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

摘要翻译： 半导体器件包括具有第一至第四区域的衬底，在第一区域中的衬底上形成的第一绝缘膜，形成在第二区域中的衬底上并具有高于第一区域的上表面的上表面的第一外延层 绝缘膜，形成在所述第一绝缘膜上的第一半导体层，其具有相对于所述第一外延层设置的空间，并且具有设置在与所述第一外延层的上表面基本相同的高度的上表面;以及元件隔离绝缘膜 膜形成在该空间中，并且具有设置在与第一外延层的上表面和第一半导体层的上表面大致相同高度的上表面。

公开(公告)号：US06906384B2

公开(公告)日：2005-06-14

申请号：US10096655

申请日：2002-03-14

申请人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

发明人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/10861 ,  H01L21/76243 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/78639

摘要： A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

摘要翻译： 半导体器件包括第一和第二半导体层以及第一和第二MOS晶体管。 第一半导体层设置在半导体衬底上并与之电连接。 第二半导体层设置在第一半导体层附近，并且经由绝缘膜和空腔中的一个形成在半导体基板的上方。 第一和第二MOS晶体管分别设置在第一和第二半导体层上，并且各自具有平行于第一和第二半导体层之间的边界排列的栅电极。

公开(公告)号：US07420249B2

公开(公告)日：2008-09-02

申请号：US11849682

申请日：2007-09-04

申请人： Tsutomu Sato ,  Hajime Nagano ,  Ichiro Mizushima ,  Takashi Yamada ,  Yuso Udo ,  Shinichi Nitta

发明人： Tsutomu Sato ,  Hajime Nagano ,  Ichiro Mizushima ,  Takashi Yamada ,  Yuso Udo ,  Shinichi Nitta

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/764 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10897 ,  H01L27/1203 ,  H01L27/1207

摘要： A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.

摘要翻译： 一种半导体器件，包括形成在半导体衬底上的第一半导体层，围绕第一半导体层的第二半导体层，在半导体衬底上形成有绝缘膜和空腔中的一个的第二半导体层和围绕 所述第二半导体层，所述第三半导体层形成在所述半导体衬底上。

公开(公告)号：US07187035B2

公开(公告)日：2007-03-06

申请号：US10237206

申请日：2002-09-09

申请人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Hisato Oyamatsu

发明人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Hisato Oyamatsu

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer deposited thinner on the semiconductor substrate than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

摘要翻译： 公开了一种制造半导体器件衬底的方法，其包括通过电绝缘层形成在半导体层与半导体衬底的表面绝缘的图案化的掩模层，根据掩模层的图案蚀刻半导体层以形成 导通绝缘层的沟槽，蚀刻比半导体衬底更薄的保护层比绝缘层的厚度形成覆盖沟槽侧表面的侧壁保护膜，从绝缘层的底表面蚀刻绝缘层 沟槽到半导体衬底; 以及从蚀刻绝缘层而暴露的半导体衬底的表面生长单晶层。

公开(公告)号：US07148543B2

公开(公告)日：2006-12-12

申请号：US10828337

申请日：2004-04-21

申请人： Takashi Yamada ,  Hajime Nagano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Hisato Oyamatsu ,  Shinichi Nitta

发明人： Takashi Yamada ,  Hajime Nagano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Hisato Oyamatsu ,  Shinichi Nitta

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L29/00 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L27/10894 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

摘要翻译： 半导体芯片包括基底基板，在基底基板的一部分上具有体积生长层的体器件区域，在基底基板上具有埋入绝缘体的SOI器件区域和埋入绝缘体上的硅层，以及边界层 位于体器件区域和SOI器件区域之间的边界处。 本体装置区域具有第一装置制造表面，其中大块装置位于本体生长层上。 SOI器件区域具有第二器件制造表面，其中SOI器件位于硅层上。 第一和第二装置制造表面被定位在基本均匀的水平。