公开(公告)号：US20080068061A1

公开(公告)日：2008-03-20

申请号：US11532295

申请日：2006-09-15

申请人： Kiyoshi Kase ,  Dzung T. Tran

发明人： Kiyoshi Kase ,  Dzung T. Tran

IPC分类号： H03H11/26

CPC分类号： H03H11/26

摘要： A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.

摘要翻译： 电路的性能可以基于诸如例如工艺，电压和/或温度的各种因素而变化。 在一个实施例中，电路包括接收输入信号的输入端子，延迟选择部分，其将输入信号延迟由性能变化指示器选择的延迟量;阻抗选择部分，其输出延迟的输入信号作为经补偿的延迟 信号，其中阻抗选择部分使用由性能变化指示器选择的驱动器阻抗量，以及输出端子，其输出经补偿的延迟信号。 电路还可以包括环形振荡器，频率计数器，其提供指示在参考频率的周期期间发生的环形振荡器的输出的上升沿的数量的计数值;以及解码器，其使用计数值 输出性能变化指标。

公开(公告)号：US20080061846A1

公开(公告)日：2008-03-13

申请号：US11530181

申请日：2006-09-08

申请人： Kiyoshi Kase ,  May Len

发明人： Kiyoshi Kase ,  May Len

IPC分类号： H03B1/00

CPC分类号： H03F3/45192 ,  H03F3/45632 ,  H03F2203/45352

摘要： An input voltage circuit comprises an input transistor having a control electrode for receiving a variable input voltage, a voltage detection transistor having a current electrode coupled to a current electrode of the input transistor forming a first node, and a current source coupled to a second current electrode of the voltage detection transistor forming a second node. The input voltage circuit further comprises a variable voltage drop transistor having a first current electrode coupled to the first node, a control electrode coupled to the second node and a second current electrode coupled to an output node, wherein the voltage detection transistor detects a variation in the variable input voltage and provides a signal to the variable voltage drop transistor. The variable voltage drop transistor generates a voltage drop proportional to the variation in the variable input voltage to ensure a substantially constant output at the output node.

摘要翻译： 输入电压电路包括具有用于接收可变输入电压的控制电极的输入晶体管，具有耦合到形成第一节点的输入晶体管的电流电极的电流电极的电压检测晶体管，以及耦合到第二电流的电流源 形成第二节点的电压检测晶体管的电极。 输入电压电路还包括可变压降晶体管，其具有耦合到第一节点的第一电流电极，耦合到第二节点的控制电极和耦合到输出节点的第二电流电极，其中电压检测晶体管检测到 可变输入电压并向可变压降晶体管提供信号。 可变压降晶体管产生与可变输入电压的变化成比例的电压降，以确保输出节点处的输出基本恒定。

公开(公告)号：US06384641B1

公开(公告)日：2002-05-07

申请号：US09873818

申请日：2001-06-04

申请人： Kiyoshi Kase

发明人： Kiyoshi Kase

IPC分类号： G11C2702

CPC分类号： G11C27/026

摘要： A signal sampling circuit and method uses a compensating capacitor (30) connected between a ground terminal and an output of an operational amplifier (12) to permit noise error to be applied to both electrodes of a separate output sampling capacitor (18). The noise error component is generated from high frequency noise coupled to the sampling capacitor via a semiconductor substrate. Compensation occurs during a sampling phase and an output operational amplifier (14) is used to filter any high frequency noise during a hold phase.

摘要翻译： 信号采样电路和方法使用连接在接地端子和运算放大器（12）的输出端之间的补偿电容器（30），以允许将噪声误差施加到单独的输出采样电容器（18）的两个电极。 噪声误差分量由经由半导体衬底耦合到采样电容器的高频噪声产生。 补偿发生在采样阶段，输出运算放大器（14）用于在保持阶段过滤任何高频噪声。

公开(公告)号：US5132895A

公开(公告)日：1992-07-21

申请号：US625519

申请日：1990-12-11

申请人： Kiyoshi Kase

发明人： Kiyoshi Kase

IPC分类号： H02M3/07

CPC分类号： H02M3/07

摘要： Two storage capacitors connected in parallel with a constant current source in a charging mode and connected in series in a second mode to increase output voltage. A comparator senses the amplitude of the output voltage and controls the current supplied to the capacitors in the charging mode to increase or decrease the output voltage to coincide with a predetermined amplitude.

摘要翻译： 两个存储电容器在充电模式下与恒流源并联连接并以第二模式串联连接以增加输出电压。 比较器感测输出电压的幅度，并且控制在充电模式下提供给电容器的电流，以增加或减小输出电压以与预定振幅一致。

公开(公告)号：US5130635A

公开(公告)日：1992-07-14

申请号：US747072

申请日：1991-08-19

申请人： Kiyoshi Kase

发明人： Kiyoshi Kase

IPC分类号： G05F1/565 ,  H03F1/02 ,  H03F3/45 ,  H03K17/04 ,  H03K17/042 ,  H03K19/0175

CPC分类号： H03K17/04206 ,  G05F1/565 ,  H03F1/0222 ,  H03F3/45076

摘要： This invention relates to a bias current control circuit which drives a power MOS transistor. Since the power MOS transistor has a large capacitance which is formed between a gate and a channel, it is needed to provide a circuit which is able to sufficiently supply a drive current to the gate. Such a circuit increases a consumption current because the circuit has to always flow the current to drive the gate. This invention provides a circuit which cut the consumption current in the circuit when the transistor is not driven, and increases a consumption current in the circuit in order to keep a gate current when the transistor is driven.

公开(公告)号：US5017805A

公开(公告)日：1991-05-21

申请号：US438910

申请日：1989-11-17

申请人： Kiyoshi Kase

发明人： Kiyoshi Kase

IPC分类号： H03M1/34 ,  H03K3/356 ,  H03K5/08

CPC分类号： H03K3/356034

摘要： A differential pair of transistors (Q2, Q3), the sources of which are connected to a current source (Q1); first and second input terminals (IN, VX) connected to the gates of the first and second transistors respectively; first and second output terminals (DN, DP) connected to the drains of the second and first transistors; third and fourth transistors (Q6, Q7), the sources of which are connected to a voltage supply (UDD), the drain of the third transistor being connected to the drain of the first transistor, and the drain of the fourth transistor being connected to the drain of the second transistor; the gate of the third transistor being connected to the drain of the first transistor via first switch (Q104) and connected to the drain of the second transistor via a first capacitor (C1); and the gate of the fourth transistor being connected to the drain of the second transistor via second switch (Q5) and connected to the drain of the first transistor via a second capacitor (C2).

公开(公告)号：US4553054A

公开(公告)日：1985-11-12

申请号：US463709

申请日：1983-02-04

申请人： Kiyoshi Kase ,  Masaru Fukuta

发明人： Kiyoshi Kase ,  Masaru Fukuta

IPC分类号： H03K3/02 ,  H03K17/22 ,  H03K5/153

CPC分类号： H03K17/223

摘要： A circuit for generating a pulse when a voltage (VDD) is applied thereto comprising an input (10) for receiving the applied voltage, an output (36), a first capacitor (16) connected to be charged from the input through a first switch (12), a second capacitor (18) connected to be charged from the first capacitor through a second switch (14), control means (34) for alternately enabling the first and second switches and switch means (20, 22, 24, 26) connected to the second capacitor for applying the applied voltage to the output when the voltage on the second capacitor is less than a predetermined value and for applying ground voltage to the output when the voltage on the second capacitor is greater than the predetermined value.

摘要翻译： 一种用于在施加电压（VDD）时产生脉冲的电路，包括用于接收所施加的电压的输入端（10），输出（36），第一电容器（16），其通过第一开关 （12），通过第二开关（14）从第一电容器连接的第二电容器（18），用于交替地使第一和第二开关和开关装置（20,22,24,26）的控制装置 ）连接到所述第二电容器，用于当所述第二电容器上的电压小于预定值时将所施加的电压施加到所述输出，并且用于当所述第二电容器上的电压大于所述预定值时将接地电压施加到所述输出。

公开(公告)号：US07768296B2

公开(公告)日：2010-08-03

申请号：US11360724

申请日：2006-02-23

申请人： Kiyoshi Kase ,  Dzung T. Tran

发明人： Kiyoshi Kase ,  Dzung T. Tran

IPC分类号： H03K19/003 ,  H03K17/16

CPC分类号： H03K19/01721

摘要： A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer output, thereby facilitating transition of a signal at the load. The current boost module can shut down the boost current before the signal at the load completes its transition from one logic state to the other.

摘要翻译： 当前升压模块接收来自缓冲器的输入和输出的信号，以确定缓冲器是否在逻辑状态之间转换。 当缓冲器正在转换时，向连接到缓冲器输出的负载提供升压电流，以补充来自缓冲器输出的电流，从而便于负载处的信号转换。 当前的升压模块可以在负载处的信号完成其从一个逻辑状态转换到另一个逻辑状态之前关闭升压电流。

公开(公告)号：US20090219093A1

公开(公告)日：2009-09-03

申请号：US12039377

申请日：2008-02-28

申请人： Kiyoshi Kase

发明人： Kiyoshi Kase

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2203/45652

摘要： An amplifier comprises an amplifier stage and an active inductor. The amplifier stage has an input terminal and an output terminal. The active inductor comprises first and second resistors and first and second transistors. The first resistor has a first terminal coupled to the output terminal of the amplifier stage, and a second terminal. The second resistor has a first terminal coupled to the output terminal of the amplifier stage, and a second terminal. The first transistor has a first current electrode coupled to the second terminal of the first resistor, a control electrode coupled to receive a bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the second terminal of the second resistor, and a second current electrode coupled to a first power supply voltage terminal.

摘要翻译： 放大器包括放大器级和有源电感器。 放大器级具有输入端和输出端。 有源电感器包括第一和第二电阻器以及第一和第二晶体管。 第一电阻器具有耦合到放大器级的输出端的第一端子和第二端子。 第二电阻器具有耦合到放大器级的输出端的第一端子和第二端子。 第一晶体管具有耦合到第一电阻器的第二端子的第一电流电极，耦合以接收偏置电压的控制电极和第二电流电极。 第二晶体管具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第二电阻器的第二端子的控制电极和耦合到第一电源电压端子的第二电流电极。

公开(公告)号：US07432754B2

公开(公告)日：2008-10-07

申请号：US11460349

申请日：2006-07-27

申请人： Kiyoshi Kase ,  Dzung T. Tran

发明人： Kiyoshi Kase ,  Dzung T. Tran

IPC分类号： H03K17/00

CPC分类号： H03K17/693 ,  H03K17/005 ,  H03K17/6871 ,  H03K2217/0036

摘要： A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

摘要翻译： 电压控制电路包括耦合到具有第一电压的第一电压源端子的第一晶体管，耦合到第一晶体管的第二晶体管和节点，耦合到第二电压源端子和节点的第三晶体管，其中第二电压 供电端子具有第二电压，并且节点处于从由第一电压和第二电压组成的组中选择的电压，以及耦合到节点的第四晶体管。