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公开(公告)号：US20170098480A1
公开(公告)日：2017-04-06
申请号：US15382394
申请日：2016-12-16
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Jeffrey Wright
IPC: G11C29/00
CPC classification number: G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
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公开(公告)号：US09558851B2
公开(公告)日：2017-01-31
申请号：US15133096
申请日：2016-04-19
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Jeffrey Wright
IPC: G11C7/00 , G11C29/00 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C11/408 , G11C29/44
CPC classification number: G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
Abstract translation: 公开了软包装修复的装置和方法。 一种这样的设备可以包括封装中的存储器单元，易失性存储器被配置为响应于进入软件后封装修复模式，匹配逻辑电路和解码器而存储有缺陷的地址数据。 匹配逻辑电路可以产生指示与要访问的地址相对应的地址数据是否与存储在易失性存储器中的检测地址数据相匹配的匹配信号。 解码器可以响应于匹配信号来选择要访问的存储器单元的第一组而不是第二组，所述匹配信号指示对应于要访问的地址的地址数据与存储在易失性存储器中的缺陷地址数据相匹配 。 存储器单元的第二组可对应于与存储在该装置的非易失性存储器中的其他缺陷地址数据相关联的替换地址。
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公开(公告)号：US20160232987A1
公开(公告)日：2016-08-11
申请号：US15133096
申请日：2016-04-19
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Jeffrey Wright
IPC: G11C29/00 , G11C29/04 , G11C11/408
CPC classification number: G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
Abstract: Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
Abstract translation: 公开了软包装修复的装置和方法。 一种这样的设备可以包括封装中的存储器单元，易失性存储器被配置为响应于进入软件后封装修复模式，匹配逻辑电路和解码器而存储有缺陷的地址数据。 匹配逻辑电路可以产生指示与要访问的地址相对应的地址数据是否与存储在易失性存储器中的检测地址数据相匹配的匹配信号。 解码器可以响应于匹配信号来选择要访问的存储器单元的第一组而不是第二组，所述匹配信号指示对应于要访问的地址的地址数据与存储在易失性存储器中的缺陷地址数据相匹配 。 存储器单元的第二组可对应于与存储在该装置的非易失性存储器中的其他缺陷地址数据相关联的替换地址。
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公开(公告)号：US20150135038A1
公开(公告)日：2015-05-14
申请号：US14077630
申请日：2013-11-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Alan J. Wilson , Jeffrey Wright
IPC: G11C29/00
CPC classification number: G11C29/76 , G11C8/06 , G11C29/789 , G11C29/802 , G11C2029/4402
Abstract: Apparatuses and methods for post package repair are disclosed. An apparatus can include memory cells in a package. A storage element can store information responsive to a post-package repair mode being activated. The information can identify an address mapped to a portion of the memory cells to be repaired. The storage element can store the information responsive to data received from nodes of the package. A walking token circuit can interrogate the information stored in the storage element in a serial fashion responsive to the post-package repair mode being activated. A mapping circuit can remap, responsive to the interrogation, the address to be repaired to another portion of the memory cells.
Abstract translation: 公开了用于后包装修复的装置和方法。 装置可以包括封装中的存储器单元。 存储元件可以存储响应于被激活的封装后修复模式的信息。 信息可以标识映射到要修复的存储器单元的一部分的地址。 存储元件可以响应于从包的节点接收的数据来存储信息。 行走令牌电路可以响应于被激活的封装后修复模式，以串行方式询问存储在存储元件中的信息。 映射电路可以根据询问将要修复的地址重新映射到存储器单元的另一部分。
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公开(公告)号：US20250094043A1
公开(公告)日：2025-03-20
申请号：US18893737
申请日：2024-09-23
Applicant: Micron Technology, Inc.
Inventor： Donald Martin Morgan , Alan J. Wilson
IPC: G06F3/06
Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.
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Patent Agency Ranking
公开(公告)号：US20250053327A1
公开(公告)日：2025-02-13
申请号：US18806210
申请日：2024-08-15
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Donald M. Morgan
Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
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公开(公告)号：US20230229304A1
公开(公告)日：2023-07-20
申请号：US18100803
申请日：2023-01-24
Applicant: Micron Technology, Inc.
Inventor： Donald Martin Morgan , Alan J. Wilson
IPC: G06F3/06
CPC classification number: G06F3/0604 , G06F3/0644 , G06F3/0679
Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.
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公开(公告)号：US11579990B2
公开(公告)日：2023-02-14
申请号：US17142828
申请日：2021-01-06
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson
Abstract: Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.
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公开(公告)号：US11557367B2
公开(公告)日：2023-01-17
申请号：US17317221
申请日：2021-05-11
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , Alan J. Wilson
Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.
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公开(公告)号：US20220291854A1
公开(公告)日：2022-09-15
申请号：US17197733
申请日：2021-03-10
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Donald M. Morgan
Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
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