公开(公告)号：US20190384512A1

公开(公告)日：2019-12-19

申请号：US16555293

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F3/06

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

公开(公告)号：US10387299B2

公开(公告)日：2019-08-20

申请号：US15214982

申请日：2016-07-20

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F12/0815 ,  G06F12/02 ,  G06F12/0855 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

公开(公告)号：US20190065082A1

公开(公告)日：2019-02-28

申请号：US15691484

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0683 ,  G11C7/065 ,  G11C7/1006

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

公开(公告)号：US20180349052A1

公开(公告)日：2018-12-06

申请号：US16025058

申请日：2018-07-02

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe ,  Harish N. Venkata

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/08 ,  G11C17/16

CPC classification number: G11C7/1012 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16

Abstract: The present disclosure includes apparatuses and methods related to a shift skip. An example apparatus comprises a plurality of sensing circuitries, comprising respective sense amplifiers and respective compute components. A controller is configured to, responsive to a mask data unit associated with a first sensing circuitry having a particular value, cause a data value to be shifted from a second sensing circuitry to a third sensing circuitry without shifting the data value to the first sensing circuitry, wherein the first sensing circuitry is physically located between the second sensing circuitry and the third sensing circuitry.

公开(公告)号：US11881245B2

公开(公告)日：2024-01-23

申请号：US17939908

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Miles S. Wiscombe ,  James S. Rehmeyer ,  Eric J. Stave

IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4076 ,  G11C5/04

CPC classification number: G11C11/406 ,  G11C5/04 ,  G11C11/4074 ,  G11C11/4076

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

公开(公告)号：US20230307033A1

公开(公告)日：2023-09-28

申请号：US17701950

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Scott E. Smith ,  Jennifer E. Taylor ,  Gary L. Howe

IPC: G06F3/06 ,  G11C11/4096 ,  G11C11/4076

CPC classification number: G06F3/061 ,  G11C11/4096 ,  G11C11/4076 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673

Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.

公开(公告)号：US20220375507A1

公开(公告)日：2022-11-24

申请号：US17881482

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Miles S. Wiscombe ,  Scott E. Smith ,  Gary L. Howe ,  Brian W. Huber ,  Tony M. Brewer

IPC: G11C11/408 ,  G11C11/4096 ,  G11C11/406

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

公开(公告)号：US11482265B2

公开(公告)日：2022-10-25

申请号：US17486481

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.

公开(公告)号：US20220148638A1

公开(公告)日：2022-05-12

申请号：US17094731

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Miles S. Wiscombe ,  James S. Rehmeyer ,  Eric J. Stave

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4076

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

公开(公告)号：US20220083239A1

公开(公告)日：2022-03-17

申请号：US17531573

申请日：2021-11-19

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/06

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.