公开(公告)号：US20190280600A1

公开(公告)日：2019-09-12

申请号：US15918960

申请日：2018-03-12

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: H02M3/335 ,  G06F1/30 ,  H01L23/498 ,  H01L23/50 ,  G11C5/14 ,  H02M1/32

Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.

公开(公告)号：US20190278496A1

公开(公告)日：2019-09-12

申请号：US15919102

申请日：2018-03-12

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F3/06 ,  G06F11/34 ,  G06F1/32

Abstract: A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.

公开(公告)号：US20190278362A1

公开(公告)日：2019-09-12

申请号：US15919036

申请日：2018-03-12

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F1/32 ,  G06F12/02 ,  G11C16/26 ,  G11C16/30 ,  G11C5/14 ,  G11C7/20 ,  G11C7/22 ,  H01L27/11521 ,  H01L27/11526

Abstract: Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.

公开(公告)号：US12081113B2

公开(公告)日：2024-09-03

申请号：US17554839

申请日：2021-12-17

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: H02M1/32 ,  G06F1/30 ,  G11C5/14 ,  H01L23/498 ,  H01L23/50 ,  H02M3/335

CPC classification number: H02M1/32 ,  G06F1/305 ,  G11C5/14 ,  H01L23/49838 ,  H01L23/50 ,  H02M1/322 ,  H02M3/33507

Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.

公开(公告)号：US11614872B2

公开(公告)日：2023-03-28

申请号：US17174211

申请日：2021-02-11

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F1/32 ,  G06F3/06 ,  G06F1/3246 ,  G06F1/3225 ,  G06F11/34

Abstract: A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.

公开(公告)号：US20230073948A1

公开(公告)日：2023-03-09

申请号：US18056092

申请日：2022-11-16

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F3/06 ,  G11C5/14

Abstract: Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

公开(公告)号：US11474705B2

公开(公告)日：2022-10-18

申请号：US16932116

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley ,  David Matthew Springberg ,  Dustin James Carter

IPC: G06F3/06 ,  G06F13/42

Abstract: Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.

公开(公告)号：US20220137698A1

公开(公告)日：2022-05-05

申请号：US17575334

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F1/3296 ,  G06F12/02 ,  G11C7/20 ,  G11C16/26 ,  G11C5/14 ,  G11C7/22 ,  G11C16/30 ,  H01L27/11526 ,  G11C7/10 ,  H01L27/11521 ,  G06F1/3234

Abstract: A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

公开(公告)号：US20220109372A1

公开(公告)日：2022-04-07

申请号：US17554839

申请日：2021-12-17

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: H02M3/335 ,  G06F1/30 ,  H02M1/32 ,  H01L23/50 ,  G11C5/14 ,  H01L23/498

Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.

公开(公告)号：US11223282B2

公开(公告)日：2022-01-11

申请号：US16397694

申请日：2019-04-29

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F1/30 ,  H02M1/32 ,  H02M3/335 ,  H01L23/50 ,  G11C5/14 ,  H01L23/498

Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.