公开(公告)号：US07247556B2

公开(公告)日：2007-07-24

申请号：US11068237

申请日：2005-02-28

申请人： Arun K. Nanda ,  Nace Rossi

发明人： Arun K. Nanda ,  Nace Rossi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.

摘要翻译： 一种制造集成电路（IC）的方法，其中通过适当地控制IC多层互连结构的层堆叠的一个或多个服务层中的固有应力来控制晶片翘曲。 在一个实施例中，多层互连结构的每个互连级别具有电介质层，形成在电介质层上的导电层，以及形成在导电层上的功能抗反射涂层（ARC）层。 每个ARC层由氮氧化硅形成，使得对应于不同互连级别的至少两个ARC层具有不同的固有应力。 每个ARC层中的固有应力的量被控制，例如通过控制层沉积期间的温度和/或气体组成。

公开(公告)号：US07005724B2

公开(公告)日：2006-02-28

申请号：US10778454

申请日：2004-02-13

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： H01L23/58

CPC分类号： H01L23/53295 ,  C23C16/401 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括上述半导体器件的集成电路。 根据本发明的原理，半导体器件可以包括衬底和位于衬底上的分级覆盖层，其中分级覆盖层包括至少两个不同的层，其中至少第二层和第二层 两个不同的层具有不同的应力值。

公开(公告)号：US08084313B2

公开(公告)日：2011-12-27

申请号：US12832110

申请日：2010-07-08

申请人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

发明人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

IPC分类号： H01L21/8238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

摘要翻译： 一种用于形成根据该方法形成的BiCMOS集成电路和结构的方法。 在用于CMOS器件的掺杂阱和栅极堆叠以及用于双极结型晶体管的集电极和基极区域之后，在发射极窗口内形成发射极层。 在发射极层上形成介电材料层，并且在蚀刻发射极层和去除蚀刻掩模期间保持原位。 在源极/漏极注入掺杂和注入源极/漏极掺杂剂的激活期间，电介质材料层进一步保持就位。 介电材料层用作热障，以限制在激活步骤期间发射体掺杂物的扩散。

公开(公告)号：US20100273301A1

公开(公告)日：2010-10-28

申请号：US12832110

申请日：2010-07-08

申请人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

发明人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

IPC分类号： H01L27/06

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

摘要翻译： 一种用于形成根据该方法形成的BiCMOS集成电路和结构的方法。 在用于CMOS器件的掺杂阱和栅极堆叠以及用于双极结型晶体管的集电极和基极区域之后，在发射极窗口内形成发射极层。 在发射极层上形成介电材料层，并且在蚀刻发射极层和去除蚀刻掩模期间保持原位。 在源极/漏极注入掺杂和注入源极/漏极掺杂剂的激活期间，电介质材料层进一步保持就位。 介电材料层用作热障，以限制在激活步骤期间发射体掺杂物的扩散。

公开(公告)号：US20090108359A1

公开(公告)日：2009-04-30

申请号：US11930728

申请日：2007-10-31

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： H01L27/105 ,  H01L29/78

CPC分类号： H01L21/76832 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate structure, (3) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, (4) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, (5) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and (6) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer.

摘要翻译： 本发明提供一种半导体器件和包括该半导体器件的集成电路。 在一个实施例中，半导体器件包括：（1）位于衬底上方的栅极结构，所述栅极结构包括栅极电介质和栅电极; （2）位于靠近栅极结构的衬底内的源极/漏极区域，（3）位于衬底上方的多层蚀刻停止器，其中该蚀刻停止件具有第一绝缘层和位于第一衬底上方的第二富硅氮化物层 绝缘层，（4）位于所述蚀刻停止点上方的电介质层，所述电介质层具有形成在其中的开口，所述开口延伸穿过所述多层蚀刻停止件的至少一部分，（5）位于所述开口内并电接触的导电插塞 栅电极和源极/漏极区之一，以及（6）位于导电插塞和第二富硅氮化物层之间的绝缘间隔物。

公开(公告)号：US20080079083A1

公开(公告)日：2008-04-03

申请号：US11930794

申请日：2007-10-31

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： H01L29/78

CPC分类号： H01L21/76831 ,  H01L21/76832 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L29/6659

摘要： The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate structure, (3) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, (4) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, (5) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and (6) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer.

摘要翻译： 本发明提供一种半导体器件和包括该半导体器件的集成电路。 在一个实施例中，半导体器件包括：（1）位于衬底上方的栅极结构，所述栅极结构包括栅极电介质和栅电极; （2）位于靠近栅极结构的衬底内的源极/漏极区域，（3）位于衬底上方的多层蚀刻停止器，其中该蚀刻停止件具有第一绝缘层和位于第一衬底上方的第二富硅氮化物层 绝缘层，（4）位于所述蚀刻停止点上方的电介质层，所述电介质层具有形成在其中的开口，所述开口延伸穿过所述多层蚀刻停止件的至少一部分，（5）位于所述开口内并电接触的导电插塞 栅电极和源极/漏极区之一，以及（6）位于导电插塞和第二富硅氮化物层之间的绝缘间隔物。

公开(公告)号：US20060194428A1

公开(公告)日：2006-08-31

申请号：US11068237

申请日：2005-02-28

申请人： Arun Nanda ,  Nace Rossi

发明人： Arun Nanda ,  Nace Rossi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.

摘要翻译： 一种制造集成电路（IC）的方法，其中通过适当地控制IC多层互连结构的层堆叠的一个或多个服务层中的固有应力来控制晶片翘曲。 在一个实施例中，多层互连结构的每个互连级别具有电介质层，形成在电介质层上的导电层，以及形成在导电层上的功能抗反射涂层（ARC）层。 每个ARC层由氮氧化硅形成，使得对应于不同互连级别的至少两个ARC层具有不同的固有应力。 每个ARC层中的固有应力的量被控制，例如通过控制层沉积期间的温度和/或气体组成。

公开(公告)号：US20050179116A1

公开(公告)日：2005-08-18

申请号：US10778454

申请日：2004-02-13

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： C23C16/40 ,  H01L21/302 ,  H01L21/316 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/53295 ,  C23C16/401 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.