公开(公告)号：US08872311B2

公开(公告)日：2014-10-28

申请号：US10778453

申请日：2004-02-13

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： H01L23/58 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L21/76831 ,  H01L21/76832 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L29/6659

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, in one particularly advantageous embodiment, includes a multi layer etch stop located over a substrate, wherein the multi layer etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer. Located over the multi layer etch stop is a dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop. A conductive plug is typically located within the opening, wherein an insulative spacer is located between the conductive plug and the second silicon-rich nitride layer.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。 在一个特别有利的实施例中，半导体器件包括位于衬底上的多层蚀刻停止件，其中多层蚀刻停止件具有位于第一绝缘层上方的第一绝缘层和第二富硅氮化物层。 位于多层蚀刻停止点上方的是具有形成在其中的开口的电介质层，其延伸穿过多层蚀刻停止件的至少一部分。 导电插塞通常位于开口内，其中绝缘垫片位于导电插塞和第二富硅氮化物层之间。

公开(公告)号：US20050282372A1

公开(公告)日：2005-12-22

申请号：US11167772

申请日：2005-06-27

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： C23C16/40 ,  H01L21/302 ,  H01L21/316 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/53295 ,  C23C16/401 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括上述半导体器件的集成电路。 根据本发明的原理，半导体器件可以包括衬底和位于衬底上的分级覆盖层，其中分级覆盖层包括至少两个不同的层，其中至少第二层和第二层 两个不同的层具有不同的应力值。

公开(公告)号：US20050179115A1

公开(公告)日：2005-08-18

申请号：US10778453

申请日：2004-02-13

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： H01L21/31 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/58

CPC分类号： H01L21/76831 ,  H01L21/76832 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L29/6659

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, in one particularly advantageous embodiment, includes a multi layer etch stop located over a substrate, wherein the multi layer etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer. Located over the multi layer etch stop is a dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop. A conductive plug is typically located within the opening, wherein an insulative spacer is located between the conductive plug and the second silicon-rich nitride layer.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。 在一个特别有利的实施例中，半导体器件包括位于衬底上的多层蚀刻停止件，其中多层蚀刻停止件具有位于第一绝缘层上方的第一绝缘层和第二富硅氮化物层。 位于多层蚀刻停止点上方的是具有形成在其中的开口的电介质层，其延伸穿过多层蚀刻停止件的至少一部分。 导电插塞通常位于开口内，其中绝缘垫片位于导电插塞和第二富硅氮化物层之间。

公开(公告)号：US07811944B2

公开(公告)日：2010-10-12

申请号：US11167772

申请日：2005-06-27

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： H01L21/31

CPC分类号： H01L23/53295 ,  C23C16/401 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括上述半导体器件的集成电路。 根据本发明的原理，半导体器件可以包括衬底和位于衬底上的分级覆盖层，其中分级覆盖层包括至少两个不同的层，其中至少第二层和第二层 两个不同的层具有不同的应力值。

公开(公告)号：US07005724B2

公开(公告)日：2006-02-28

申请号：US10778454

申请日：2004-02-13

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： H01L23/58

CPC分类号： H01L23/53295 ,  C23C16/401 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括上述半导体器件的集成电路。 根据本发明的原理，半导体器件可以包括衬底和位于衬底上的分级覆盖层，其中分级覆盖层包括至少两个不同的层，其中至少第二层和第二层 两个不同的层具有不同的应力值。

公开(公告)号：US20090108359A1

公开(公告)日：2009-04-30

申请号：US11930728

申请日：2007-10-31

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： H01L27/105 ,  H01L29/78

CPC分类号： H01L21/76832 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate structure, (3) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, (4) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, (5) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and (6) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer.

摘要翻译： 本发明提供一种半导体器件和包括该半导体器件的集成电路。 在一个实施例中，半导体器件包括：（1）位于衬底上方的栅极结构，所述栅极结构包括栅极电介质和栅电极; （2）位于靠近栅极结构的衬底内的源极/漏极区域，（3）位于衬底上方的多层蚀刻停止器，其中该蚀刻停止件具有第一绝缘层和位于第一衬底上方的第二富硅氮化物层 绝缘层，（4）位于所述蚀刻停止点上方的电介质层，所述电介质层具有形成在其中的开口，所述开口延伸穿过所述多层蚀刻停止件的至少一部分，（5）位于所述开口内并电接触的导电插塞 栅电极和源极/漏极区之一，以及（6）位于导电插塞和第二富硅氮化物层之间的绝缘间隔物。

公开(公告)号：US20080079083A1

公开(公告)日：2008-04-03

申请号：US11930794

申请日：2007-10-31

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： H01L29/78

CPC分类号： H01L21/76831 ,  H01L21/76832 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L29/6659

摘要： The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate structure, (3) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, (4) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, (5) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and (6) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer.

摘要翻译： 本发明提供一种半导体器件和包括该半导体器件的集成电路。 在一个实施例中，半导体器件包括：（1）位于衬底上方的栅极结构，所述栅极结构包括栅极电介质和栅电极; （2）位于靠近栅极结构的衬底内的源极/漏极区域，（3）位于衬底上方的多层蚀刻停止器，其中该蚀刻停止件具有第一绝缘层和位于第一衬底上方的第二富硅氮化物层 绝缘层，（4）位于所述蚀刻停止点上方的电介质层，所述电介质层具有形成在其中的开口，所述开口延伸穿过所述多层蚀刻停止件的至少一部分，（5）位于所述开口内并电接触的导电插塞 栅电极和源极/漏极区之一，以及（6）位于导电插塞和第二富硅氮化物层之间的绝缘间隔物。

公开(公告)号：US20050179116A1

公开(公告)日：2005-08-18

申请号：US10778454

申请日：2004-02-13

申请人： Nace Rossi ,  Alvaro Maury

发明人： Nace Rossi ,  Alvaro Maury

IPC分类号： C23C16/40 ,  H01L21/302 ,  H01L21/316 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/53295 ,  C23C16/401 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

公开(公告)号：US08685861B2

公开(公告)日：2014-04-01

申请号：US11462036

申请日：2006-08-02

申请人： Chih Ping Yong ,  Peter Chew ,  Chuin Boon Yeap ,  Hoon Lian Yap ,  Ranbir Singh ,  Nace Rossi ,  Jovin Lim

发明人： Chih Ping Yong ,  Peter Chew ,  Chuin Boon Yeap ,  Hoon Lian Yap ,  Ranbir Singh ,  Nace Rossi ,  Jovin Lim

IPC分类号： H01L21/311

CPC分类号： H01L21/76801 ,  H01L21/76804 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.

摘要翻译： 一种集成电路系统，包括提供集成电路器件，在所述集成电路器件上形成未掺杂绝缘层，在所述未掺杂绝缘层上形成薄绝缘层，在所述薄绝缘层上形成掺杂绝缘层，以及在所述绝缘层上形成接触 未掺杂的绝缘层，薄绝缘层和掺杂绝缘层。

公开(公告)号：US20080014728A1

公开(公告)日：2008-01-17

申请号：US11427494

申请日：2006-06-29

申请人： Nace Rossi ,  Ranbir Singh

发明人： Nace Rossi ,  Ranbir Singh

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/32051 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion of the thickness of the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer imparts a stress to the first portion that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the thickness of the metal layer is then deposited over the stress-compensating layer.

摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方法包括提供半导体衬底并在半导体衬底上沉积总厚度为约1微米或更大的金属层。 通过在半导体衬底上沉积具有与其相关的压缩或拉伸应力的金属层的厚度的第一部分来形成金属层。 应力补偿层沉积在第一部分上，使得应力补偿层向与第一部分相关联的压缩或拉伸应力相反的第一部分赋予应力。 然后将金属层的厚度的第二部分沉积在应力补偿层上。